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AgeCommit message (Expand)Author
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-03-19mem: Move bind() and unbind() into the Port class.Gabe Black
2019-03-19sim: Add a getPort function to SimObject.Gabe Black
2019-03-15mem: Move the Port base class into sim.Gabe Black
2019-03-12sim: Add size to array unserialization error messageDaniel R. Carvalho
2019-02-19sim: Add a mechanism to exit the simulation loop immediately.Gabe Black
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2019-02-12python: Fix native module initialisation on Python 3Andreas Sandberg
2019-02-08kern,sim: implement FUTEX_WAKE_OPMoyang Wang
2019-02-08sim, kern: support FUTEX_CMP_REQUEUEMoyang Wang
2019-02-08sim: handle the case when there're not enough HW thread contextsTuan Ta
2019-02-08sim,cpu: make exit_group halt all threads in a groupTuan Ta
2019-02-08sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET opsTuan Ta
2019-02-08cpu: fixed how O3 CPU executes an exit system callTuan Ta
2019-02-07arch-riscv: Enable support for riscv 32-bit in SE mode.Austin Harris
2019-02-06sim: added missed macro definition on MacOSAndrea Mondelli
2019-01-31sim: Prepare C++ side for Python 3Andreas Sandberg
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
2019-01-22sim-se add readv and modifies writevBrandon Potter
2019-01-22sim-se: add ability to get/set sock metadataBrandon Potter
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
2019-01-22sim-se: add calls for network transmissionsBrandon Potter
2019-01-22sim-se: add socket-based functionalityBrandon Potter
2019-01-18base: Fix unitialized storageDaniel R. Carvalho
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
2019-01-10sim-se, arch-arm: Add support for getdents64Javier Setoain
2019-01-10sim-se: Refactor clone to avoid most ifdefsAndreas Sandberg
2019-01-10sim-se: Correctly calculate next PC in cloneAndreas Sandberg
2019-01-10sim-se: Use CONFIG_CLONE_BACKWARDS for ArmAndreas Sandberg
2018-12-05arch-x86: Add sys/syscall.h to x86 process.cc/syscall_emul.ccTony Gutierrez
2018-12-04base, sim: Add missing destructorsNikos Nikoleris
2018-11-27sim-se: only implement getdentsFunc on supported hostsCiro Santilli
2018-11-20sim: Deschedule existing events when destructing an event queue.Gabe Black
2018-11-14sim: Move BitUnion overloading to show/parseParamsGiacomo Travaglini
2018-11-14sim: Move paramIn/Out definition to header fileGiacomo Travaglini
2018-11-12sim: Push the global frequency management code into C++.Gabe Black
2018-10-30syscall_emul: fix openat when directory does not end in "/"Ciro Santilli
2018-10-01sim: Extend (UN)SERIALIZE_ARRAY to BitUnionsGiacomo Travaglini
2018-09-19syscall_emul: implement dir-related syscallsBrandon Potter
2018-09-19syscall_emul: refactor FDEntry and children classesBrandon Potter
2018-09-19syscall_emul: style changes and FDArray refactorBrandon Potter
2018-09-19syscall_emul: expand AuxVector classBrandon Potter
2018-09-14power: Add a clock_period variable to power expressionsSherif Elhabbal
2018-09-11base: Correct a small typo in sim/core.(hh|cc).Gabe Black
2018-09-07sim: Add System method for MasterID lookupGiacomo Travaglini
2018-06-25syscall_emul: adding symlink system callMatt Sinclair
2018-06-25syscall_emul: adding link system callMatt Sinclair
2018-05-30dev: Exit correctly in dist-gem5 for SE modeMichael LeBeane
2018-05-16style: fix amd license and style issuesTony Gutierrez
2018-05-09sim: Remove trailing dot when assigning a master's nameGiacomo Travaglini
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