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2020-01-09base: Include some required headers in amo.hh.Gabe Black
amo.hh was using several non-default definitions including std::function, uint8_t, and std::array without including any headers at all, and instead apparently relying on those having already been brought in by an earlier include. This change adds those includes explicitly. Change-Id: I92166ff581e74bd705e10fd4fa454df179ae1a97 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24183 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-09base, gpu-compute: Move gpu AMOs into the generic headerGiacomo Travaglini
Change-Id: I10d8aeaae83c232141ddd2fd21ee43bed8712539 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23565 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-08arch, base: Move arm AtomicOpFunctor into the generic headerGiacomo Travaglini
These AtomicGenericxOp functors are not arm specific: They just define a set of different functors depending on the number of operands they are using. Change-Id: Ida75066823c7718aee05717194cdb8225b700c5d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23564 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-08base: Move AtomicOpFunctors to a dedicated headerGiacomo Travaglini
src/base/types.hh file definition is: /** * @file * Defines global host-dependent types: * Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t. */ I feel AtomicOpFunctor doesn't fall in this cathegory so I am moving those into a dedicated header: base/amo.hh Change-Id: I8f05fb0944c03e4053cfaf2ffe65cac803df1d93 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23563 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07arch,sim: Promote the m5ops_base param to the System base class.Gabe Black
This mechanism is shared between ARM and x86, even if x86 has a typical address range it choses to use. By moving this to the base class, it's now possible for anybody to find out where the m5 ops are, and no ISA specific assumptions need to be made. Because the x86 address is well known, it's set in the x86 System subclass as the default. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Ifdb9f5cd1ce38b3c4dafa7566c50f245f14cf790 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23180 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07cpu: Disable O3CPU value forwarding with write strobesGabor Dozsa
https://gem5-review.googlesource.com/c/public/gem5/+/19173 did the same for MinorCPU Change-Id: I22d631a3d2032570f6e84b0f5eb018d1f84414ef Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23952 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07cpu: Use enums for O3CPU store value forwardingGabor Dozsa
This is aligning with MinorCPU, where an enum is tagging a Full, Partial and No address coverage. Change-Id: I0e0ba9b88c6f08c04430859e88135c61c56e6884 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23951 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07misc: Reflect changes of arm bootloader nameAdrian Herrera
With https://gem5-review.googlesource.com/c/public/gem5/+/22687 the VExpress_GEM5_Base platform is changing the required bootloader name by removing the _emm suffix. While this had been changed in the prebuilt binaries in gem5.org, it hadn't in the bootloader makefiles or in other utility functions. The patch is not completely removing the _emm bootloaders since those are still used by VExpress_EMM and VExpress_EMM64 platforms. Change-Id: Iea3148eab313ab06cf2e74660e11708e1a22ce5f Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Adrian Herrera <adrian.herrera@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23947 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07mem-cache: Forward snoops when the cache is not respondingNikos Nikoleris
When the MSHR is handling a request that will make the block dirty the current cache commits respond. When that's not the case the cache should forward any snoops. This CL fixes MSHR::handleSnoop() to implement this behavior. Change-Id: I207e3ca4968fd9528fd4cdbfb3eb95f470b4744d Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23668 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2020-01-07mem-cache: Ensure that responses get data from the right sourceNikos Nikoleris
This CL makes sure that we use the right source for data for responses after a response from the cache below. Change-Id: I7329f3e6bcb7ce2054e912eb9dea48c9d169d45a Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23667 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07systemc: fix gem5_to_tlm bridgeEarl Ou
The original implementation doesn't set trans and phase correctly when scheduling PayloadEvent, and causes unexpected behavior after the event started. This change fixes the wrong event triggering by directly applying tlm_utils::peq instead of creating another one. Change-Id: I207567b57f4b49c3c4ebe117d624e5cc9915c12a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23823 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-07fastmodel: Implement the vecPredReg accessor functions.Gabe Black
Change-Id: Iaf6f7d8d1db427bfd486e4bd43f67cc006751873 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23789 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2020-01-07arch,sim: Stop decoding the pseudo inst subfunc value.Gabe Black
This isn't used by anything any more. The func field is left in place to ensure compatability, but there's no reason to decode a value nobody is going to use. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I85fcd0e4a362551c29af6bff350d99af86050415 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23179 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2020-01-06arch,sim: Use the guest ABI mechanism with pseudo instructions.Gabe Black
Right now, there are only two places which call the pseudoInst function directly, the ARM KVM CPU and the generic mmapped IPR. These two callers currently use the generic "PseudoInstABI" which is just a wrapper around the existing getArgument function. In the future, this getArgument function will be disolved, and the PseudoInstABI will be defined for each ABI. Since it currently mimics the Linux ABI since gem5 can only handle one ABI at a time right now, this implementation will probably be shared by linux system calls, except that the pseudo inst implementation will eat return values since those are returned through other means when the pseudo inst is based on magic address ranges. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: Ied97e4a968795158873e492289a1058c8e4e411b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23178 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-06arch-arm: Semihosting, specify files root dirAdrian Herrera
This patch adds an option to "ArmSemihosting" which allows for specifying an optional search path for host files. Previously, behaviour was fixed to search in the directory from where the gem5 binary was run from. Change-Id: I57b932b38d022f132af78857104633d7bfdd1442 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23903 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-06dev-arm: Fix SMMUv3 walkMasks in page table opsMichiel van Tol
The masks did not include the high bits above the active addressing bits. This could cause overlapping issues when using high addresses. (Translated with TTBR1) Change-Id: Ib705558aac456c1b3f069e1bd3ccdd9229a1c1d2 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23764 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-06dev-arm: Fix SMMUv3 16KB next-level table address maskingGiacomo Travaglini
The next-level table address for a granule size of 16KB is retrieved from the 47:14 bits of the current table descriptor (instead of 47:12, which is the valid masking for a 4KB granule) Change-Id: I570138a34003dc034d8e67dc1209316157d57205 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel van Tol <michiel.vantol@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23763 Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-06dev-arm: GICv3, handle GICR_ICFGR0 WI behaviourAdrian Herrera
Architecture states write accesses to GICR_ICFGR0 are WI. This patch implements handling of this behaviour instead of crashing as an invalid offset. This is required to support certain software behaviour. Change-Id: I1f8c57838566c360d243a925306ec35c64a920b2 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24063 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-06mem-cache: Avoid write merging if there are reads in betweenNikos Nikoleris
This CL reworks the logic in the MSHR to make sure we do not coalesce requests unless there is a series of write requests for the whole cache block without any other incompatible requests (e.g., read) in between. Change-Id: I0b3195858fb33ef85d7aae27376506057dd53ea7 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23666 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-03sim: Move destructor of Port to publicYu-hsin Wang
To preventing from instantiating an abstract class, hiding its constructor is enough. Moving destructor to public doesn't break this intention. This also makes us can use smart pointer to manage derived Port class. Change-Id: Ic9cf97e90a6c26108d359eb459df48cd23eaf15c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23925 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-03cpu: Fix issue with MinorCPU predicated-false mem. accessesGiacomo Gabrielli
The code block was relying on passed_predicate only (conditional execution). This was not covering the case where the instruction gets executed, but the predicate register is false. Using the inLSQ variable is covering both cases and it makes more sense in terms of readibility. Change-Id: Ie1954f37968379a5bda9d0dc9f824a68304cc229 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23280 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-03cpu: Disable MinorCPU value forwarding with write strobesGabor Dozsa
Change-Id: I7cb50b80b70fcf43ab23eb9e7333d16328993fe1 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19173 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-30fastmodel: Fix compilation errorsChun-Chen TK Hsu
This changes fixes two compilation errors when compiling with FastModels. One is that CurrentMsn should be Iris::CurrentMsn and the other is that currEL() function needs arch/arm/utility.hh header file. Test by compiling GEM5 with FastModels: scons -j64 build/ARM/gem5.opt \ USE_ARM_FASTMODEL=1 \ PVLIB_HOME=... \ MAXCORE_HOME=... \ ARMLMD_LICENSE_FILE=... \ Change-Id: Iabe0a5f25246591f99b57219428b8f87ecd3363c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23924 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-27fastmodel: Move ARM but not CortexA76 specific bits to the IRIS TC.Gabe Black
Now that the IRIS thread context can be specific to ARM, some things which had been pushed to a different level of abstraction can be mvoed back. This will hopefully allow more code sharing in the future when other types of CPUs are supported. Change-Id: Ic3a5f0db53ebe93e18f7507ed71812bce27b6d01 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23788 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-27fastmodel: Move the ARM IRIS threadcontext into CortexA76.Gabe Black
This specialization will correspond specifically with the CortexA76, instead of specializing the ThreadContext for ARM in general. Some aspects of this class may need to move into the base IRIS thread context class, but I'll leave that for a later change. Change-Id: I9cbe527d36e6fda78601dc39c1963370cfa28b16 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23787 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-27fastmodel: Mostly collapse ARM base classes for the CortexA76 CPU.Gabe Black
Fast models are in practice only ARM, so it's not that helpful to have the ARM-ness factored out. It is, however, helpful to have aspects which control how gem5 concepts like registers are mapped to fast model concepts like resources, especially since these mappings may vary from fast model to fast model. For instance, it looks like the CortexA76 does not have predicate vector registers. Rather than make all fast models support or not support those registers, that can be done on a model by model basis. Change-Id: I195da4a2f4d2f8593032d0d63e9fd3d20a240d01 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23786 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-27fastmodel: Checkpoint the TCs when checkpointing a fast model CPU.Gabe Black
The generic thread context checkpointing code can be used which calls into the ThreadContext methods to read the required state. Change-Id: Ib5c318ff4d2e756274b4c90b56533b2689a837f2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23785 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-27fastmodel: Handle "special" vector regs without calling into IRIS.Gabe Black
These registers don't have an architectural equivalent, but they may need to be accessed by generic code, for instance the code that checkpoints a thread context. Change-Id: I4a18f44f2c09e379a4629c8e3eb8070b5c01918e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23784 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-24fastmodel: Implement readVecRegFlat for ArmThreadContext.Gabe Black
This just calls readVecReg after constructing a RegId. Change-Id: Ia26b9bb874fec62f98bd5e4d3c6aa1059766c2f6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23783 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-24fastmodel: Determine what space to use for breakpoints dynamically.Gabe Black
This was hardcoded as 5, but should be determined based on the memory space IDs the fast model returns. What we do now is have a specific override for ARM (perhaps conceptually the A76) which looks for an address space called "Current" which seems to work well. It's possible that the appropriate address space for a different model might have a different number, or even a different name. This may need to be further specialized/parameterized in those cases. Change-Id: Ie1ef99675fd9bccab50b7fc7add16b82a93bd60b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22143 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-23fastmodel: Implement PC based events.Gabe Black
These use the IRIS breakpoint API to stop the models at the appropriate points. There seems to be a slightly wonky interaction between breakpoints and stepping, where if you stop at a breakpoint and then step, you might end up moving forward more than the number of requested instructions. Change-Id: I31f13a120cfc1ad2ec3669ee8befd6d21b328bb2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22122 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-21base: Fix negative op-assign of SatCounterDaniel R. Carvalho
The value of the add and subtract assignment operations can be negative, and this was not being handled properly previously. Regarding shift assignment, the standard says it is undefined behaviour if a negative number is given, so add assertions for these cases. Change-Id: I2f1e4143c6385caa80fb25f84ca8edb0ca7e62b7 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23664 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-20configs: arm realview(64) regressions using VExpress_GEM5_V1Giacomo Travaglini
This patch is updating the arm regression configs so that the newer VExpress_GEM_V1 platform is used instead of the older VExpress_EMM and VExpress_EMM64. A new optional kernel_mode argument has been added in order to distinguish between realview and realview64 platforms. If not provided the config will assume the machine is running a AArch64 kernel. Other notable additions: - DTB autogeneration in regressions - Using minimal m5exit.squashfs disk image Change-Id: Ia230565f072fe3eb7756c41876dba4657583f4df Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22687 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-12-20systemc: Fix tlm2 socket integrationJui-min Lee
This change will make the systemc extension in gem5 more compatible to the reference implementation by Accellera. * Remove the alias of sc_port's bind in initiator socket. * Ignore -Woverloaded-virtual in initiator socket. Change-Id: I229e4d493e01d26174c5662ad71d4859d546d307 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23864 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-20arch-arm: Fix clang warningsJui-min Lee
Fix some warnings reported by clang. * missing override in {freebsd,linux}/process.hh Change-Id: I67c36a0785ac90614211d640fd58d3ffe187c17e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23863 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-19arch-arm: Fix decoding of LDFF1x scalar plus scalarAdrià Armejach
First-faulting loads do allow Rm == 0x1f. Change-Id: Ib9bcb55e126653813fdbb7c29970af23a2471ebb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23803 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18arch-arm: Semihosting, fix SYS_FLENAdrian Herrera
SYS_FLEN was incorrectly handled as SYS_ISTTY. This patch fixes this behaviour. Change-Id: I66e0b97d8b44d2cb78e0b1bb940fd6f4b52c658f Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23752 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18sim: kernelExtras optional load addressesAdrian Herrera
This patch provides a new "System" parameter named "kernel_extras_addrs". This allows to optionally specify fixed load addresses for the additional kernel objects. This is useful to load arbitrary blobs into memory. Change-Id: I4725763b86c29f72282d1c184d4284d90f9d3016 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23566 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18python: fix "fatal" usage in fdthelperAdrian Herrera
"fatal" was not correctly imported in the fdthelper module, which caused a crash when reporting errors. Change-Id: I7ee9dcde1f0288e11e56dba67ead4aa2d6d67e02 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23753 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18arch-arm: Secure EL2 checkingAdrian Herrera
This patch adds Armv8.4-SecEL2 checking. Helpers implementing EL2Enabled, IsSecureEL2Enabled and HaveSecureEL2Ext following the architecture pseudocode are provided. These are intended to be used for checking register access permissions. Change-Id: I3d06d0127cf165c1eeaf3302830742d610cef719 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23766 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18arch-arm: AArch64 trap check, arbitrary ECs/ImmsAdrian Herrera
This patch generalises trap checking when accessing system registers in AArch64. Depending on the accessed register, a different Exception Class (EC) and immediate value may be set. Previously this only took SIMD traps into account. Change-Id: I30717676a210c770531e39e4c6a6e1fbfdfdc583 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23765 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-18x86: Fix some bugs with KVM in SE mode on Intel machines.Gabe Black
The granularity bit should be set since the segment limit should be interpreted as a number of pages, not bytes. A comment indicates that NX support is enabled, but the bit wasn't being set. That's now set to be consistent with FS mode. The SVME bit is now turned off, since Intel CPUs don't have SVME, and enabling it apparently makes them upset. Also disable CR4 bits which enable features neither gem5 nor apparently my workstation support. Change-Id: I72d5a07871dede8763b0dd188a52fe5eb6bde6ea Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23361 Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17sim: Include some required headers in the syscall debug macros header.Gabe Black
Everything that includes syscall_debug_macros.hh and uses the macro in it will need these headers, so they should be included through syscall_debug_macros.hh. The consumer shouldn't have to know what the macros use internally and to include extra headers to support them. Change-Id: I9bfa932368daec0772d552357ecad8790b4cfead Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23459 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-12-17fastmodel: Tell fast model not to shutdown when time stops.Gabe Black
Change-Id: I000e7809a2c8850eb31e5615caf1d88b537fea8d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22121 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Implement port proxies.Gabe Black
This plumbing is simple and largely copied from other implementations within gem5. This mechanism should be refactored so that the duplication is unnecessary. Change-Id: Ibcdf759b7fba1d574e8e2ba04249afdd92c6560c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22120 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Create a TLB model which uses IRIS to do translations.Gabe Black
Change-Id: I806dc8cdacce57e6ec31d2421b9e6b9733c7da02 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22119 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-12-17fastmodel: Add an address translation mechanism to the ThreadContext.Gabe Black
This will be used by the TLB to do the actual translation. Unfortunately there isn't a great way to tell what translation type to use, so we just go through all of them for now. The ARM subclass might specialize and figure out which address spaces to use based on control register state. Change-Id: Id1fcad66554acf9d69af683917b3c2834f825da0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22118 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17base: Fix AddrRange::isSubset() checkNikos Nikoleris
Making _end non-inclusive, introduced a bug in isSubset() which was checking if _end is included in the input address range. This CL changes the behavior and now we test if _end - 1 is in the range. Change-Id: Ib8822472b7c266e10d55f3d5cf22a46aa45c1fc7 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23663 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17scons: Added channel_addr.cc dependency to channel_addr GTestBobby R. Bruce
In some circumstances not including channel_addr.cc as a dependency for the channel_addr.test compilation resulted in a build failure (this was observed in gem5's Kokoro CI system). This commit fixes this problem. Change-Id: Ic38a104a1e6bf655fc64158b556e6227d5ac3981 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23603 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-17fastmodel: Add a header for IRIS MSN constants.Gabe Black
Change-Id: I06a7d7db95ec1ce65945c9e09f812f0b69aaa8e6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23643 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 16:42:47 +0000