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2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2 src/cpu/base_dyn_inst.hh: Hand merge. Line is no longer needed because it's handled in the ISA. --HG-- extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
2007-03-23Make hardware loads/stores serializing; they need to avoid certain ↵Kevin Lim
out-of-order interactions in the 21264. --HG-- extra : convert_revision : d83940af7d0e8efe891d574ac42c6d70d179e2b1
2007-03-23Updates for commit.Kevin Lim
1. Move interrupt handling to a separate function to clean up main commit() function a bit. Also gate the function call off properly based on whether or not there are outstanding interrupts, and the system is not in PAL mode. 2. Better handling of updating instruction's status bits. Instructions are not marked "atCommit" until other stages view it (pushed off to IEW/IQ), and they have been properly handled (faults). 3. Don't consider the ROB "empty" for the purpose of other stages until the ROB is empty, all stores have written back, and there was no store commits this cycle. The last is necessary in case a store committed, in which case it would look like all stores have written back but in actuality have not. src/cpu/o3/commit.hh: Slightly modify how interrupts are handled. Also include some extra bools to keep track of state properly. src/cpu/o3/commit_impl.hh: Slightly modify how interrupts are handled. Also include some extra bools to keep track of state. General correctness updates, most specifically for when commit broadcasts to other stages that the ROB is empty. --HG-- extra : convert_revision : 682ec6ccf4ee6ed0c8a030ceaba1c90a3619d102
2007-03-233 memory system fixes:Kevin Lim
1. Update packet's flags properly when a snoop happens 2. Don't allow accesses to read a block's data if the block has outstanding MSHRs. This avoids a RAW hazard in MP systems that the memory system was not detecting properly earlier (a write required a block to upgrade, and while the upgrade was outstanding, a read came along and read old data). 3. Update MSHR's request upon a response being handled. If the MSHR has more targets than it can respond to in one cycle, then its request must be properly updated to the new head of the targets list. src/mem/bus.cc: Update packet's flags properly upon snoop. src/mem/cache/cache_impl.hh: Be sure to not allow accesses to a block with outstanding MSHRs. src/mem/cache/miss/miss_queue.cc: Update MSHR's request upon a response being handled. --HG-- extra : convert_revision : 76a9abc610ca3f1904f075ad21637148a41982d6
2007-03-23Handle status bits a little better, as well as non-speculative instructions.Kevin Lim
src/cpu/o3/iew_impl.hh: Allow for slightly more flexible handling of non-speculative instructions. They can be other classes now, such as loads or stores. Also be sure to clear the state associated with squashes that are not used. i.e. if a squash due to a memory ordering violation happens on the same cycle as an older branch squashing, clear the state associated with the memory ordering violation. Lastly don't consider uncached loads to officially be "at commit" until IEW receives the signal back from commit about the load. src/cpu/o3/inst_queue_impl.hh: Don't consider non-speculative instructions to be "at commit" until the IQ has received a signal from commit about the instruction. This prevents non-speculative instructions from being issued too early. src/cpu/o3/mem_dep_unit_impl.hh: Clear instruction's ability to issue if it's replayed. --HG-- extra : convert_revision : d69dae878a30821222885485f4dee87170d56eb3
2007-03-23Two fixes:Kevin Lim
1. Requests are handled more properly now. They assume the memory system takes control of the request upon sending out an access. 2. load-load ordering is maintained. src/cpu/base_dyn_inst.hh: Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out. Also include some functions to allow certain status bits to be cleared. src/cpu/base_dyn_inst_impl.hh: Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out. src/cpu/o3/fetch_impl.hh: General correctness fixes. retryPkt is not necessarily always set, so handle it properly. Also consider the cache unblocked only when recvRetry is called. src/cpu/o3/lsq_unit.hh: Handle requests a little more correctly. Now that the requests aren't pointed to by the DynInst, be sure to delete the request if it's not being used by the memory system. Also be sure to not store-load forward from an uncacheable store. src/cpu/o3/lsq_unit_impl.hh: Check to make sure load-load ordering was maintained. Also handle requests a little more correctly. --HG-- extra : convert_revision : e86bead2886d02443cf77bf7a7a1492845e1690f
2007-03-23Set progress_interval in terms of CPU cycles.Kevin Lim
--HG-- extra : convert_revision : 76b0918276cb613eb314ab1479b5ffdb31f31dee
2007-03-23A couple of minor fixes.Kevin Lim
1. Set CPU ID in all modes for the O3 CPU. 2. Use nextCycle() function to prevent phase drift in O3 CPU. 3. Remove assertion in rename map that is no longer true. src/cpu/o3/alpha/cpu_builder.cc: Allow for CPU id in all modes, not just full system. Also include a parameter that was left out by accident. src/cpu/o3/alpha/cpu_impl.hh: Set the CPU ID properly. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: Use nextCycle() function so that the CPU does not get out of phase when starting up from quiesces. src/cpu/o3/rename_map.cc: Remove assertion that is no longer true. tests/configs/o3-timing.py: Set CPU's id to 0. --HG-- extra : convert_revision : 2b69c19adfce2adcc2d1939e89d702bd6674d5d5
2007-03-22Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : fd590d464359d8ae859998a9f446b960781a5e33
2007-03-22finish up the coding of the Intel Gb NIC... Many Many bugs to squashAli Saidi
src/dev/i8254xGBe.cc: src/dev/i8254xGBe.hh: src/dev/i8254xGBe_defs.hh: finish coding the Intel Gb NIC device src/dev/io_device.hh: we really don't want to be able to pass a null buffer to dma read, at least not the way we have things setup now... it won't work at all --HG-- extra : convert_revision : 6739497232317ec407cfa7a96de4575a9a6cfc46
2007-03-22Add structure based bitfield syntax to the isa_parser. This is primarily ↵Gabe Black
useful for x86. --HG-- extra : convert_revision : dfe6df160d00adec1830d9b88520ba20834d1209
2007-03-22Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 79c337f18d635acc176f0ca8d6e71fbc429cb258
2007-03-21Add a junk operand. With no operands, the parser breaks.Gabe Black
--HG-- extra : convert_revision : 7410fd3681ed3d9b1293d982ed5f3553a6c75f3f
2007-03-21Start implementing groups of instructions which do the same thing on ↵Gabe Black
different sets of inputs. --HG-- extra : convert_revision : 6a5be61831588f801965dd4e80cb52f28911c320
2007-03-21put the int register count in intregs.hhGabe Black
--HG-- extra : convert_revision : c48c13d9c4606c8cb7c60d18cd0f4dac9103a501
2007-03-21Break out the one and two byte opcodes into different files. Also change ↵Gabe Black
what bits decode is done on to reflect where clumps of instructions are. --HG-- extra : convert_revision : 8768676eac25e6a4f0dc50ce2dc576bdcdd6e025
2007-03-21Missed a constGabe Black
--HG-- rename : src/arch/x86/isa/decoder.isa => src/arch/x86/isa/decoder/decoder.isa extra : convert_revision : a60e7495da6fe99fa2375a3f801f2962c3e41adb
2007-03-21Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace --HG-- extra : convert_revision : 41214c71e7fa11d47395975a141793337d020463
2007-03-21The m5 side of statetrace. This is fairly ugly, but I don't want to lose it.Gabe Black
--HG-- extra : convert_revision : 171b41418567c1f41f43363a46fa9aeaa58ae606
2007-03-20Ignore "time" and "times" syscalls.Gabe Black
--HG-- extra : convert_revision : 3ff55e35877c0fd74823ce5e52ed16c38da92068
2007-03-20Fixed up some types and const placement, and added signed bitfields that ↵Gabe Black
sign extend themselves. --HG-- extra : convert_revision : 84bda8fc14f9a6f7dc7982c9aeb15bf688457706
2007-03-20Added syntax for structure oriented extMachInsts.Gabe Black
--HG-- extra : convert_revision : 4a30c58019ad8e3dd8dffb4c4c08eb6914e5c5be
2007-03-19Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : a6ae6ce183aaa4d1a9434f9ddd64cc30878d2147
2007-03-19Ditched read or write only subbitfields for now since they were proving ↵Gabe Black
difficult to implement. Allow component Bitfields to be instantiated without templates, clean up the implementation a little, and adjust the comments to match. --HG-- extra : convert_revision : b9b8aea285a95eeabbb4c0233c1bce49b8c773b8
2007-03-19For the _BitfieldRO and _BitfieldWO classes, make sure the undesired ↵Gabe Black
operator is redefined as private. --HG-- extra : convert_revision : b18d8e49547c2712ab255d048850c5231313b80a
2007-03-19Formatting fixes.Gabe Black
--HG-- extra : convert_revision : 276d0667daa4626288b56af3b4b17a3f9052e81a
2007-03-19Lots and lots of comments.Gabe Black
--HG-- extra : convert_revision : 0de510464e2e002775ccd79e2922ccb0055845e5
2007-03-19Reworked the BitUnion stuff a bit. There is moderately better isolation of ↵Gabe Black
the backend parts, although there are still macros. --HG-- extra : convert_revision : e9692c5e697c96061ef70cf78ef532c99dbbd672
2007-03-18Compile fixes for SPARC_FS.Gabe Black
src/arch/alpha/predecoder.hh: src/arch/sparc/predecoder.hh: Put in a missing include src/cpu/exetrace.cc: Convert the legion lockstep stuff from makeExtMI to the predecoder object. --HG-- extra : convert_revision : 91bad4466f8db1447fff8608fa46a5f236dc3a89
2007-03-17Created BitUnion type which lets you define nested bitfields for an integer ↵Gabe Black
in a portable way. --HG-- extra : convert_revision : 56a9d06b6b7274a493dae4b290c5f9b42e59f20d
2007-03-16Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 3246c58850586b880641638bedb1f0025d0ef491
2007-03-16Fix ALPHA_FS compile. The MachInst -> StaticInstPtr constructor is no longer ↵Gabe Black
a conversion constructor because it caused ambiguous conversions when setting the pointer to NULL. --HG-- extra : convert_revision : ce9ecfc03a47642d105f2378208bbe923d6b765b
2007-03-16Make the SPARC branch instructions use ExtMachInsts in their constructors. ↵Gabe Black
This isn't necessary since they don't use the extended fields, but it's more consistent and more correct. --HG-- extra : convert_revision : afd4f408122ad5e497012eb9744d6bce66a1de37
2007-03-15Merge zizzer:/bk/newmemAli Saidi
into pb15.local:/Users/ali/work/m5.newmem --HG-- extra : convert_revision : 0aa2fadf8978ae30ebe4fde03c525e6b9115117a
2007-03-15fix a bug gabe foundAli Saidi
--HG-- extra : convert_revision : 12e8f09f6c59a16b2d2eb78bdd1345fc38c4de40
2007-03-15Refactor things a little.Gabe Black
--HG-- extra : convert_revision : 8167455ffc05130d4afcc68466879c7c439bee57
2007-03-15File with the predecoder in it.Gabe Black
src/arch/x86/predecoder.cc: File for the x86 predecoder process function. --HG-- extra : convert_revision : f7b53c38ff152cb2677d641074218ffd8434457b
2007-03-15Split the x86 "process" predecoder method into it's own file.Gabe Black
--HG-- extra : convert_revision : 88185e592df2a7527d36efcce7376fb05f469cbc
2007-03-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : cf2cc07f18b877f980e2d1fc83916f7849d9c7d9
2007-03-15Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 6a75fa02391c4c65063c5412a568705bb1dd892b
2007-03-15add all the registers we'll need to support for the Intel GbE device and ↵Ali Saidi
support enough functionality make the driver think the device is there, and in good working order. src/dev/SConscript: add intel gbe to the dev SCons file src/dev/i8254xGBe.cc: src/dev/i8254xGBe.hh: src/dev/i8254xGBe_defs.hh: use new manner of registers and implement all device registers that are touched through boot and ifup --HG-- extra : convert_revision : b1a1767f0fd31cd371e432cb48ac9a2e9f9291b5
2007-03-15Changed warns to DPRINTFs and multiply by 8 where needed.Gabe Black
--HG-- extra : convert_revision : 9db0bc2420ceb5828a79881fa0b420a2d5e5f358
2007-03-15Added immediate value support, and fixed alot of bugs. This won't support 3 ↵Gabe Black
byte opcodes. --HG-- extra : convert_revision : 4c79bff2592a668e1154916875f019ecafe67022
2007-03-15Compile fixGabe Black
--HG-- extra : convert_revision : 4a66d04404beee9656e3e33089afcec10d7ee5ff
2007-03-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 src/arch/mips/utility.hh: src/arch/x86/SConscript: Hand merge --HG-- extra : convert_revision : 0ba457aab52bf6ffc9191fd1fe1006ca7704b5b0
2007-03-15Make the predecoder an object with it's own switched header file. Start ↵Gabe Black
adding predecoding functionality to x86. src/arch/SConscript: src/arch/alpha/utility.hh: src/arch/mips/utility.hh: src/arch/sparc/utility.hh: src/cpu/base.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/static_inst.hh: src/arch/alpha/predecoder.hh: src/arch/mips/predecoder.hh: src/arch/sparc/predecoder.hh: Make the predecoder an object with it's own switched header file. --HG-- extra : convert_revision : 77206e29089130e86b97164c30022a062699ba86
2007-03-13fix segfault when peer owner attempts to use functional portAli Saidi
--HG-- extra : convert_revision : 3702b4bd038a59bff823c3b428fdfbaabc9715df
2007-03-13Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace --HG-- extra : convert_revision : 61eca737296a5ce839d3b97f047b4fda062cb899
2007-03-13Replaced makeExtMI with predecode.Gabe Black
Removed the getOpcode function from StaticInst which only made sense for Alpha. Started implementing the x86 predecoder. --HG-- extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
2007-03-13fix interrupting during a quisce on sparcAli Saidi
src/arch/sparc/ua2005.cc: fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to check if were suspended and interrupt at the guess time src/base/traceflags.py: add trace flag for Iob src/cpu/simple/base.cc: Use Quisce instead of IPI trace flag src/dev/sparc/iob.cc: add some Dprintfs --HG-- extra : convert_revision : 72e18fcc750ad1e4b2bb67b19b354eaffc6af6d5
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