gem5 - gem5

Age	Commit message (Expand)	Author
2019-10-29	mem-cache: Do not try to compress dataless packets	Daniel R. Carvalho
2019-10-29	mem: Fix DRAM controller to operate on its own address space	Nikos Nikoleris
2019-10-29	mem-cache: Avoid promotion of incompatible deferred targets	Nikos Nikoleris
2019-10-29	mem-cache: Fix MSHR whole line write tracking	Nikos Nikoleris
2019-10-28	tests, base: Fixed incorrect implementation of StrTest.ToLower test.	Bobby R. Bruce
2019-10-25	mips,riscv: Get rid of some Alpha cruft in these System classes.	Gabe Black
2019-10-25	cpu: Get rid of the nextInstEventCount method.	Gabe Black
2019-10-25	cpu: Get rid of the serviceInstCountEvents method.	Gabe Black
2019-10-25	fastmodel: Use getCurrentInstCount for totalInsts().	Gabe Black
2019-10-25	fastmodel: Implement getCurrentInstCount.	Gabe Black
2019-10-25	cpu: Switch off of the CPU's comInstEventQueue.	Gabe Black
2019-10-25	cpu: Access inst events through ThreadContext instead of the CPU.	Gabe Black
2019-10-25	cpu: Delegate comInstEventQueue methods to the ThreadContexts.	Gabe Black
2019-10-25	cpu: Make accesses to comInstEventQueue indirect through methods.	Gabe Black
2019-10-25	cpu,sim: Delegate PCEvent scheduling from Systems to ThreadContexts.	Gabe Black
2019-10-25	cpu: Make the ThreadContext a PCEventScope.	Gabe Black
2019-10-25	cpu,sim: Get rid of a bunch of conditional compilation for PCEvents.	Gabe Black
2019-10-25	cpu: Don't print the CPU name when a (Break\|Panic)PCEvent happens.	Gabe Black
2019-10-25	cpu: Pass the address to check into the PCEventQueue service method.	Gabe Black
2019-10-25	sim: Make the System object a PCEventScope.	Gabe Black
2019-10-25	cpu: Stop checking for PC changes when servicing a PCEventQueue.	Gabe Black
2019-10-25	cpu: Create a PCEventScope class to abstract the scope of PCEvents.	Gabe Black
2019-10-24	tests: Added GTests for base/str.cc	Bobby R. Bruce
2019-10-24	cpu, sim-se: don't wake up threads that are awake in futex	Ciro Santilli
2019-10-24	sim-se: fix futexFunc TGT_FUTEX_WAIT always selects bitset	Ciro Santilli
2019-10-23	fastmodel: Add string constructors which delegate to const char * ones.	Gabe Black
2019-10-23	cpu: Apply the ARM TLB rework to the O3 checker CPU.	Gabe Black
2019-10-23	arch: Drop sysctl support if built against glibc	Tommaso Marinelli
2019-10-22	configs: Clean setupBootLoader signature	Giacomo Travaglini
2019-10-22	dev-arm, configs: Using _on_chip_memory for on chip memory	Giacomo Travaglini
2019-10-21	cpu: Apply the ARM TLB rework to the checker CPU.	Gabe Black
2019-10-19	cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs.	Gabe Black
2019-10-19	arch: Remove the "interrupts.hh" switching header file.	Gabe Black
2019-10-19	arch: Make a base class for Interrupts.	Gabe Black
2019-10-18	dev-arm: Check for gem5 extensions in GicV2	Tiago Muck
2019-10-18	tests: Added GTests for base/bitfield.hh	Bobby R. Bruce
2019-10-18	arch: Get rid of the unused GenericTLB.	Gabe Black
2019-10-18	cpu: Turn the stage 2 ARM MMUs from params to children.	Gabe Black
2019-10-18	x86: Turn the local APIC Interrupts class into a SimObject.	Gabe Black
2019-10-18	tests: Added GTests for base/atomicio.cc	Bobby R. Bruce
2019-10-18	base: Add classes that encapsulate a channel address	Andreas Sandberg
2019-10-18	mem: Delete the MessageReq and MessageResp memory commands.	Gabe Black
2019-10-17	arm: Don't force the ArmISA::TLB in vtophys.cc.	Gabe Black
2019-10-17	cpu: Clean up some style issues in pc_event.(hh\|cc).	Gabe Black
2019-10-17	cpu: Get rid of load count based events.	Gabe Black
2019-10-16	base: Add addIntlvBits to AddrRange	Andreas Sandberg
2019-10-16	base: Using scoped string in DPRINTFNR	Giacomo Travaglini
2019-10-16	base: Fix gem5.fast compilation	Giacomo Travaglini
2019-10-16	arch,base,sim: Move Process loader hooks into the Process class.	Gabe Black
2019-10-15	x86: Use a std::function to handle MSI completion.	Gabe Black