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2013-02-19scons: Add warning for overloaded virtual functionsAndreas Hansson
A derived function with a different signature than a base class function will result in the base class function of the same name being hidden. The parameter list and return type for the member function in the derived class must match those of the member function in the base class, otherwise the function in the derived class will hide the function in the base class and no polymorphic behaviour will occur. This patch addresses these warnings by ensuring a unique function name to avoid (unintentionally) hiding any functions.
2013-02-19scons: Add warning for missing field initializersAndreas Hansson
This patch adds a warning for missing field initializers for both gcc and clang, and addresses the warnings that were generated.
2013-02-19scons: Fix up numerous warnings about name shadowingAndreas Hansson
This patch address the most important name shadowing warnings (as produced when using gcc/clang with -Wshadow). There are many locations where constructor parameters and function parameters shadow local variables, but these are left unchanged.
2013-02-19mem: Enforce strict use of busFirst- and busLastWordTimeAndreas Hansson
This patch adds a check to ensure that the delay incurred by the bus is not simply disregarded, but accounted for by someone. At this point, all the modules do is to zero it out, and no additional time is spent. This highlights where the bus timing is simply dropped instead of being paid for. As a follow up, the locations identified in this patch should add this additional time to the packets in one way or another. For now it simply acts as a sanity check and highlights where the delay is simply ignored. Since no time is added, all regressions remain the same.
2013-02-19mem: Change accessor function names to match the port interfaceAndreas Hansson
This patch changes the names of the cache accessor functions to be in line with those used by the ports. This is done to avoid confusion and get closer to a one-to-one correspondence between the interface of the memory object (the cache in this case) and the port itself. The member function timingAccess has been split into a snoop/non-snoop part to avoid branching on the isResponse() of the packet.
2013-02-19mem: Make packet bus-related time accounting relativeAndreas Hansson
This patch changes the bus-related time accounting done in the packet to be relative. Besides making it easier to align the cache timing to cache clock cycles, it also makes it possible to create a Last-Level Cache (LLC) directly to a memory controller without a bus inbetween. The bus is unique in that it does not ever make the packets wait to reflect the time spent forwarding them. Instead, the cache is currently responsible for making the packets wait. Thus, the bus annotates the packets with the time needed for the first word to appear, and also the last word. The cache then delays the packets in its queues before passing them on. It is worth noting that every object attached to a bus (devices, memories, bridges, etc) should be doing this if we opt for keeping this way of accounting for the bus timing.
2013-02-19mem: Add deferred packet class to prefetcherAndreas Hansson
This patch removes the time field from the packet as it was only used by the preftecher. Similar to the packet queue, the prefetcher now wraps the packet in a deferred packet, which also has a tick representing the absolute time when the packet should be sent.
2013-02-19sim: Make clock private and access using clockPeriod()Andreas Hansson
This patch makes the clock member private to the ClockedObject and forces all children to access it using clockPeriod(). This makes it impossible to inadvertently change the clock, and also makes it easier to transition to a situation where the clock is derived from e.g. a clock domain, or through a multiplier.
2013-02-19x86: Move APIC clock divider to PythonAndreas Hansson
This patch moves the 16x APIC clock divider to the Python code to avoid the post-instantiation modifications to the clock. The x86 APIC was the only object setting the clock after creation time and this required some custom functionality and configuration. With this patch, the clock multiplier is moved to the Python code and the objects are instantiated with the appropriate clock.
2013-02-19mem: Fix SenderState related cache deadlockSascha Bischoff
This patch fixes a potential deadlock in the caches. This deadlock could occur when more than one cache is used in a system, and pkt->senderState is modified in between the two caches. This happened as the caches relied on the senderState remaining unchanged, and used it for instantaneous upstream communication with other caches. This issue has been addressed by iterating over the linked list of senderStates until we are either able to cast to a MSHR* or senderState is NULL. If the cast is successful, we know that the packet has previously passed through another cache, and therefore update the downstreamPending flag accordingly. Otherwise, we do nothing.
2013-02-19mem: Add predecessor to SenderState base classAndreas Hansson
This patch adds a predecessor field to the SenderState base class to make the process of linking them up more uniform, and enable a traversal of the stack without knowing the specific type of the subclasses. There are a number of simplifications done as part of changing the SenderState, particularly in the RubyTest.
2013-02-19base: Fix a bug in the address interleavingAndreas Hansson
This patch fixes a minor (but important) typo in the matching of an address to an interleaved range.
2013-02-19mem: Ensure trace captures packet fields before forwardingAndreas Hansson
This patch fixes a bug in the CommMonitor caused by the packet being modified before it is captured in the trace. By recording the fields before passing the packet on, and then putting these values in the trace we ensure that even if the packet is modified the trace captures what the CommMonitor saw.
2013-02-15loader: add a flattened device tree blob (dtb) objectAnthony Gutierrez
this adds a dtb_object so the loader can load in the dtb file for linux/android ARM kernels.
2013-02-15arm: fix a page table walker issue where a page could be translated multiple ↵Mrinmoy Ghosh
times If multiple memory operations to the same page are miss the TLB they are all inserted into the page table queue and before this change could result in multiple uncessesary walks as well as duplicate enteries being inserted into the TLB.
2013-02-15cpu: Document exec trace flagsAndreas Sandberg
2013-02-15dev: Use the correct return type for disk offsetsAndreas Sandberg
Replace the use of off_t in the various DiskImage related classes with std::streampos. off_t is a signed 32 bit integer on most 32-bit systems, whereas std::streampos is normally a 64 bit integer on most modern systems. Furthermore, std::streampos is the type used by tellg() and seekg() in the standard library, so it should have been used in the first place. This patch makes it possible to use disk images larger than 2 GiB on 32 bit systems with a modern C++ standard library.
2013-02-15cpu: Avoid duplicate entries in tracking structures for writes to misc regsGeoffrey Blake
setMiscReg currently makes a new entry for each write to a misc reg without checking for duplicates, this can cause a triggering of the assert if an instruction get replayed and writes to the same misc regs multiple times. This fix prevents duplicate entries and instead updates the value.
2013-02-15cpu: Fix rename mis-handling serializing instructions when resource constrainedGeoffrey Blake
The rename can mis-handle serializing instructions (i.e. strex) if it gets into a resource constrained situation and the serializing instruction has to be placed on the skid buffer to handle blocking. In this situation the instruction informs the pipeline it is serializing and logs that the next instruction must be serialized, but since we are blocking the pipeline defers this action to place the serializing instruction and incoming instructions into the skid buffer. When resuming from blocking, rename will pull the serializing instruction from the skid buffer and the current logic will see this as the "next" instruction that has to be serialized and because of flags set on the serializing instruction, it passes through the pipeline stage as normal and resets rename to non-serializing. This causes instructions to follow the serializing inst incorrectly and eventually leads to an error in the pipeline. To fix this rename should check first if it has to block before checking for serializing instructions.
2013-02-15ARM: Postpones creation of framebuffer output file until it is actually used.Chris Emmons
This delay prevents a potential conflict with the HDLCD if both are in the same system even if only one is enabled.
2013-02-15mem: Tighten up cache constness and scopingAndreas Hansson
This patch merely adopts a more strict use of const for the cache member functions and variables, and also moves a large portion of the member functions from public to protected.
2013-02-15base: Add warn() and inform() to m5.utils for use from pythonSascha Bischoff
This patch adds two fuctions to m5.util, warn and inform, which mirror those found in the C++ side of gem5. These are added in addition to the already existing m5.util.panic and m5.util.fatal which already mirror the C++ functionality. This ensures that warning and information messages generated by python are in the same format as those generated by C++. Occurrences of print "Warning: %s..." % name have been replaced with warn("%s...", name)
2013-02-15o3: fix tick used for renaming and issue with range selectionMatt Horsnell
Fixes the tick used from rename: - previously this gathered the tick on leaving rename which was always 1 less than the dispatch. This conflated the decode ticks when back pressure built in the pipeline. - now picks up tick on entry. Added --store_completions flag: - will additionally display the store completion tail in the viewer. - this highlights periods when large numbers of stores are outstanding (>16 LSQ blocking) Allows selection by tick range (previously this caused an infinite loop)
2012-10-25arm: Don't export private GIC methodsAndreas Sandberg
2012-10-25arm: Create a GIC base class and make the PL390 derive from itAndreas Sandberg
This patch moves the GIC interface to a separate base class and makes all interrupt devices use that base class instead of a pointer to the PL390 implementation. This allows us to have multiple GIC implementations. Future implementations will allow in-kernel GIC implementations when using hardware virtualization. --HG-- rename : src/dev/arm/gic.cc => src/dev/arm/gic_pl390.cc rename : src/dev/arm/gic.hh => src/dev/arm/gic_pl390.hh
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
Virtualized CPUs and the fastmem mode of the atomic CPU require direct access to physical memory. We currently require caches to be disabled when using them to prevent chaos. This is not ideal when switching between hardware virutalized CPUs and other CPU models as it would require a configuration change on each switch. This changeset introduces a new version of the atomic memory mode, 'atomic_noncaching', where memory accesses are inserted into the memory system as atomic accesses, but bypass caches. To make memory mode tests cleaner, the following methods are added to the System class: * isAtomicMode() -- True if the memory mode is 'atomic' or 'direct'. * isTimingMode() -- True if the memory mode is 'timing'. * bypassCaches() -- True if caches should be bypassed. The old getMemoryMode() and setMemoryMode() methods should never be used from the C++ world anymore.
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
CPUs need to test that the memory system is in the right mode in two places, when the CPU is initialized (unless it's switched out) and on a drainResume(). This led to some code duplication in the CPU models. This changeset introduces the verifyMemoryMode() method which is called by BaseCPU::init() if the CPU isn't switched out. The individual CPU models are responsible for calling this method when resuming from a drain as this code is CPU model specific.
2013-02-15config: Move CPU handover logic to m5.switchCpus()Andreas Sandberg
CPU switching consists of the following steps: 1. Drain the system 2. Switch out old CPUs (cpu.switchOut()) 3. Change the system timing mode to the mode the new CPUs require 4. Flush caches if switching to hardware virtualization 5. Inform new CPUs of the handover (cpu.takeOverFrom()) 6. Resume the system m5.switchCpus() previously only did step 2 & 5. Since information about the new processors' memory system requirements is now exposed, do all of the steps above. This patch adds automatic memory system switching and flush (if needed) to switchCpus(). Additionally, it adds optional draining to switchCpus(). This has the following implications: * changeToTiming and changeToAtomic are no longer needed, so they have been removed. * changeMemoryMode is only used internally, so it is has been renamed to be private. * switchCpus requires a reference to the system containing the CPUs as its first parameter. WARNING: This changeset breaks compatibility with existing configuration scripts since it changes the signature of m5.switchCpus().
2013-02-15cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchyAndreas Sandberg
Checker CPUs currently don't inherit from the CheckerCPU in the Python object hierarchy. This has two consequences: * It makes CPU model discovery from the Python world somewhat complicated as there is no way of testing if a CPU is a checker. * Parameters are duplicated in the checker configuration specification. This changeset makes all checker CPUs inherit from the base checker CPU class.
2013-02-15cpu: Add CPU metadata om the Python classesAndreas Sandberg
The configuration scripts currently hard-code the requirements of each CPU. This is clearly not optimal as it makes writing new configuration scripts painful and adding new CPU models requires existing scripts to be updated. This patch adds the following class methods to the base CPU and all relevant CPUs: * memory_mode -- Return a string describing the current memory mode (invalid/atomic/timing). * require_caches -- Does the CPU model require caches? * support_take_over -- Does the CPU support CPU handover?
2013-02-15arm: fix some fp comparisons that worked by accident.Ali Saidi
The explict tests in the follwing fp comparison operations were incorrect as they checked for only signaling NaNs and not quite-NaNs as well. When compiled with gcc, the comparison generates a fp exception that causes the FE_INVALID flag to be set and we check for it, so even though the check was incorrect, the correct exception was set. With clang this behavior seems to not occur. The checks are updated to test for nans and the behavior is now correct with both clang and gcc.
2013-02-15cpu: include set in o3/commit_impl.Ali Saidi
While the majority of compilers seemed to pickup set from else where, one version of gcc 4.7 complains, so explictly add it.
2013-02-15ARM: Fix an issue with clang generating wrong code.Ali Saidi
Clang generated executables would enter the if condition when it wasn't supposted to, resulting in the wrong simulated behavior. Implementing the operation this way is a bit faster anyway.
2013-02-15cpu: fix case with o3 cpu blocking and unblocking decode in cycleAli Saidi
Fix a case in the O3 CPU where the decode stage blocks and unblocks in a single cycle sending both signals to fetch which causes an assert or worse. The previous check could never work before since the status was set to Blocked before a test for the status being Unblocking was executed.
2013-02-15cpu: Fix a livelock in the o3 cpu.Ali Saidi
Check if an instruction just enabled interrupts and we've previously had an interrupt pending that was not handled because interrupts were subsequently disabled before the pipeline reached a place to handle the interrupt. In that case squash now to make sure the interrupt is handled.
2013-02-10base: Add support for newer versions of IPythonAndreas Sandberg
IPython is used for the interactive gem5 shell if it exists. IPython made API changes in version 0.11. This patch adds support for IPython version 0.11 and above. --HG-- extra : rebase_source : 5388d0919adb58d97f49a1a637db48cba61283a3
2013-02-14Ruby: Fix compilation errors on gcc 4.7 and clang 3.2Andreas Hansson
This patch fixes a few (recently added) errors that prevented gem5 from compiling on more recent versions of gcc and clang.
2013-02-10ruby: MI protocol: add a missing transitionNilay Vaish
The transition for state MII and event Store was found missing during testing. The transition is being added. The controller will not stall the Store request in state MII
2013-02-10ruby: enable multiple clock domainsNilay Vaish
This patch allows ruby to have multiple clock domains. As I understand with this patch, controllers can have different frequencies. The entire network needs to run at a single frequency. The idea is that with in an object, time is treated in terms of cycles. But the messages that are passed from one entity to another should contain the time in Ticks. As of now, this is only true for the message buffers, but not for the links in the network. As I understand the code, all the entities in different networks (simple, garnet-fixed, garnet-flexible) should be clocked at the same frequency. Another problem is that the directory controller has to operate at the same frequency as the ruby system. This is because the memory controller does not make use of the Message Buffer, and instead implements a buffer of its own. So, it has no idea of the frequency at which the directory controller is operating and uses ruby system's frequency for scheduling events.
2013-02-10ruby: replace Time with Cycles (final patch in the series)Nilay Vaish
This patch is as of now the final patch in the series of patches that replace Time with Cycles.This patch further replaces Time with Cycles in Sequencer, Profiler, different protocols and related entities. Though Time has not been completely removed, the places where it is in use seem benign as of now.
2013-02-10ruby: replace Time with Cycles in garnet fixed and flexibleNilay Vaish
2013-02-10ruby: replace Time with Tick in replacement policy classesNilay Vaish
2013-02-10ruby: convert block size, memory size to unsignedNilay Vaish
2013-02-10ruby: replace Time with Cycles in MessageBufferNilay Vaish
2013-02-10ruby: replace Time with Cycles in Memory ControllerNilay Vaish
2013-02-10ruby: Replace Time with Cycles in SequencerMessageNilay Vaish
2013-02-10ruby: replace Time with Cycles in Message classNilay Vaish
Concomitant changes are being committed as well, including the io operator<< for the Cycles class.
2013-02-10ruby: replaces Time with Cycles in many placesNilay Vaish
The patch started of with replacing Time with Cycles in the Consumer class. But to get ruby to compile, the rest of the changes had to be carried out. Subsequent patches will further this process, till we completely replace Time with Cycles.
2013-02-10base: add some mathematical operators to Cycles classNilay Vaish
2013-02-10ruby: modifies histogram add() functionNilay Vaish
This patch modifies the Histogram class' add() function so that it can add linear histograms as well. The function assumes that the left end point of the ranges of the two histograms are the same. It also assumes that when the ranges of the two histogram are changed to accomodate an element not in the range, the factor used in changing the range is same for both the histograms. This function is then used in removing one of the calls to the global profiler*. The histograms for recording the delays incurred in processing different requests are now maintained by the controllers. The profiler adds these histograms when it needs to print the stats.