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2019-06-13base: AddrRange does not merge single interleaved rangesTiago Muck
AddrRange does not attempt to merge interleaved address ranges if it has only one of the ranges. This is needed to allow XBars to accept request targeting only one part of a interleaved address range. A use case for this would be modeling distributed LLCs in which a XBar is used solely to encapsulate the snoop filter of a single LLC slice. Change-Id: If71c9cf1444ee11916611afb51eab3a4f1d93985 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18788 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-11cpu: Additional TrafficGen statsTiago Muck
Additional stats to keep track of read/write latencies and throughput. Change-Id: I7684cd33cf68fffdef4ca9c3a6db360a0f531c18 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18418 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-11cpu: Limit TrafficGen outstanding reqsTiago Muck
Parameter to limit the number of requests waiting for a response. Change-Id: I6cf9e8782a06ae978fb66f7c4278f4c9e9980c79 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18417 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-11cpu: TrafficGen as BaseCPUTiago Muck
TrafficGen has additional attributes to behave like a BaseCPU. Python scripts that expect sim. objects derived from BaseCPU can now be used with TrafficGen without additional modifications. Change-Id: Iee848b2ba0ac1851c487b1003da9bd96253d291a Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18416 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-10python: Fix cxx_ini_parse for ScopedEnumNikos Nikoleris
Change-Id: I69534bbbc16b2d24a65fa1dee4926f213c3618ef Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19152 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-10python: Add binding for the new AddrRange c++ constructorNikos Nikoleris
Change-Id: I5b3fb59a11d8587a753759310dd3b2748ac13a0b Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19132 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-10base: Extend unit tests for AddrRangeNikos Nikoleris
Change-Id: Ia154c3a17c3c8254a0e3d622568ac34f0d62fc9e Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19131 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-10base: Extend AddrRange to support more flexible addressingNikos Nikoleris
Previously an AddrRange could express interleaving using a number of consecutive bits and in additional optionally a second number of consecutive bits. The two sets of consecutive bits would be xored and matched against a value to determine if an address is in the AddrRange. For example: sel[0] = a[8] ^ a[12] sel[1] = a[9] ^ a[13] where sel == intlvMatch This change extends AddrRange to allow more flexible interleavings with an abritary number of set of bits which do not need be consecutive. For example: sel[0] = a[8] ^ a[11] ^ a[13] sel[1] = a[15] ^ a[17] ^ a[19] where sel == intlvMatch Change-Id: I42220a6d5011a31f0560535762a25bfc823c3ebb Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19130 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2019-06-10base: Fix ctz32 for systems where unsigned int is not 32bitNikos Nikoleris
The implementation of ctz32 uses __builtin_ctz to count the number of trailing zeros and therefore makes the assumption that an unsigned int is 32bit. This change checks whether that's the case and if not it uses __builtin_ctzl instead. Change-Id: Ic3ed3ada25fd0a93c7eb91d75b954e9924bdbb77 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19129 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-10base: Add function to count trailing zeros in a 64-bit integerNikos Nikoleris
Change-Id: Iaad0679b403bc5015ffeacbf7284313e41a36cd0 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19128 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-10arch-arm: implement VMINNM scalar thumbCiro Santilli
VMINNM was implemented at Iabbbca2932557cf6c98ce36690c385c3ddf39ed8 but the thumb scalar encoding was missing. This patch implements it. Change-Id: Ia29ec77dbd82f6be6b3d040a0e737794f52c33bf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19108 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-09base: Provide a getter for Fiber::started boolean variableGiacomo Travaglini
This can be used to check if the fiber has started its execution. Change-Id: Ie9222b8076756363c9f82c1333c76a352bcaf817 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18648 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-09base: Rename TestFiber into SwitchingFiberGiacomo Travaglini
This is done since TestFiber is too generic and it is not the only Fiber's testing subclass in the unit test Change-Id: Idc386f487091ae9bdadae865090a6719a25583da Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19153 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-07arch-arm: Fix WalkerState,Descriptors default constructorGiacomo Travaglini
Those POD strutures are not initializing all members at construction. This could lead to undefined behaviour Change-Id: Iaa8afb126382b6bfbef686883a026262f24d5ca1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Javier Setoain <javier.setoain@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19149 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-06dev-arm: Implement a SMMUv3 modelStanislaw Czerniawski
This is an implementation of the SMMUv3 architecture. What can it do? - Single-stage and nested translation with 4k or 64k granule. 16k would be straightforward to add. - Large pages are supported. - Works with any gem5 device as long as it is issuing packets with a valid (Sub)StreamId What it can't do? - Fragment stage 1 page when the underlying stage 2 page is smaller. S1 page size > S2 page size is not supported - Invalidations take zero time. This wouldn't be hard to fix. - Checkpointing is not supported - Stall/resume for faulting transactions is not supported Additional contributors: - Michiel W. van Tol <Michiel.VanTol@arm.com> - Giacomo Travaglini <giacomo.travaglini@arm.com> Change-Id: Ibc606fccd9199b2c1ba739c6335c846ffaa4d564 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19008 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-06mem: Option to toggle DRAM low-power statesMatthew Poremba
Adding an option to enable DRAM low-power states. The low power states can have a significant impact on application performance (sim_ticks) on the order of 2-3x, especially for compute-gpu apps. The options allows for it to easily be enabled/disabled to compare performance numbers. The option is disabled by default. Change-Id: Ib9bddbb792a1a6a4afb5339003472ff8f00a5859 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18548 Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-05mem-ruby: Enable set size increaseJohn Alsop
Add NUMBER_BITS_PER_SET environment variable to control the size of the bitmask in Set.hh (default=64). Necessary for configs which require >64 instances of a given machine type. This can be set in the build_opts file, e.g. by adding the following line: NUMBER_BITS_PER_SET = <number> Change-Id: I314a3cadca8ce975fcf4a60d9022494751688e88 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18968 Reviewed-by: Tiago Mück <tiago.muck@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-04base: Fix missing headers to CircularQueueDaniel R. Carvalho
CircularQueue is currently throwing compilation errors when creating a derived class. assert() needs <cassert> ptrdiff_t needs <cstddef> (u)intX_t need <cstdint> random_access_iterator_tag needs <iterator> is_same, enable_if and others need <type_traits> Change-Id: I77a78e7b13f7a8b8e7e8b2b872065d78d1ab815a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19089 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-04Revert "mem-cache: Remove writebacks packet list"Daniel Carvalho
This reverts commit bf0a722acdd8247602e83720a5f81a0b69c76250. Reason for revert: This patch introduces a bug: The problem here is that the insertion of block A may cause the eviction of block B, which on the lower level may cause the eviction of block A. Since A is not marked as present yet, A is "safely" removed from the snoop filter However, by reverting it, using atomic and a Tags sub-class that can generate multiple evictions at once becomes broken when using Atomic mode and shall be fixed in a future patch. Change-Id: I5b27e54b54ae5b50255588835c1a2ebf3015f002 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19088 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-03cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)Javier Bueno
Described by the following article: Jiménez, D. "Multiperspective perceptron predictor." Championship Branch Prediction (CBP-5) (2016). Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15495 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-31x86: fix movsd bug on %xmm registerBrandon Potter
The movsd instruction should zero out half the register, but does not do it. This changeset adds the necessary microop to the instruction to cause correct behavior. Change-Id: I5278da3634c78a97ed0586f687a36c6dc5a34c60 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19068 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-31arm: Fix decoding of CRC32 instructions in thumb32Chun-Chen TK Hsu
The CRC32 and CRC32C instructions are incorrectly decoded in thumb32 mode according to the latest manual: https://developer.arm.com/docs/ddi0597/latest/top-level-encodings-for-t32/16-bit#dpint_2r Change-Id: I9c6684f1ec7fe14d3b4cdf13f117a9819e046578 Signed-off-by: Chun-Chen TK Hsu Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19028 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-31cpu-o3: Increase LSQ buffer sizes to match max vector lengthGabor Dozsa
Change-Id: I5890c7cfa147125ce3389001f85d56d4b5a9911d Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13525 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-05-31arch-arm: Treat SVE prefetch instructions as no-opsGiacomo Gabrielli
Change-Id: Ife0424e274dd65d6dc4f6e5cc5e37d17b03be0d8 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13522 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-30arch-arm: Add initial support for SVE gather/scatter loads/storesGiacomo Gabrielli
Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13521 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-30cpu: Fix rescheduling of progress check eventsTiago Muck
noRequestEvent needs to be rescheduled on recvRetry, otherwise the timeout may be triggered even though packets are being eventually sent. noResponseEvent scheduling is also fixed. This timeout should not be active when we are not expecting a response. Change-Id: If9edb75b5b803caf9f99bf41ea3948b15a3f3d71 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18793 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-30arch: Add include guards to auto-gen. decode headerGiacomo Gabrielli
Change-Id: I03bfc9035b82bc1a42e799cf645d43cb5dafb4cb Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18911 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-30cpu-o3: Add support for pinned writesGiacomo Gabrielli
This patch adds support for pinning registers for a certain number of consecutive writes. This is only relevant for timing CPU models (functional-only models are unaffected), and it is primarily needed to provide a realistic execution model for micro-coded operations whose microops can write to non-overlapping portions of a destination register, e.g. vector gather loads. In those cases, this mechanism can disable renaming for a sequence of consecutive writes, thus making the resulting execution more efficient: allocating a new physical register for each microop would introduce a read-modify-write chain of dependencies, while with these modifications the microops can write back in parallel. Please note that this new feature is only leveraged by O3CPU for the time being. Additional authors: - Gabor Dozsa <gabor.dozsa@arm.com> Change-Id: I07eb5fdbd1fa0b748c9bdc1174d9f330fda34f81 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13520 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-30arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.Gabe Black
These two functions were performing the same function but had two different names for historical reasons. This change merges them together, keeping the getVirtProxy name to be consistent with the getPhysProxy method used to get a non-translating proxy port. Change-Id: Idd83c6b899f9343795075b030ccbc723a79e52a4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18581 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-30cpu: Store the translating proxy with the same pointer in SE or FS mode.Gabe Black
Only one is active at a time, so they can share the same pointer. Change-Id: Ie4ae1f0ffbf9448f6730f9c7d072bc85d6d423da Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18580 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-05-30cpu, sim: Return PortProxy &s from all the proxy accessors.Gabe Black
This is a step towards merging the accessors for SE and FS modes. Change-Id: I76818ab88b97097ac363e243be9cc1911b283090 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18579 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-30kern: Replace an explicitly instantiated port proxy with one from the tc.Gabe Black
That avoids having to know what type of proxy to create. Change-Id: I311e770ab720061b52f29df0dcc2273e028aa34a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18578 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-30arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.Gabe Black
Al(most) all of the interesting differences between the two classes have been removed. There are some control methods which are still specific to each type which may require treating them as their true type, but most code that consumes them doesn't need to worry about which is which. Change-Id: Ie592676f1e496c7940605b66e55cd7fae18e59d6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18577 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-30mem: Remove the now unused Copy* methods from the FS port proxy.Gabe Black
Change-Id: Ie433a9e4c9ee748911060eb7b1b47e617aa297a6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18576 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-30arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.Gabe Black
This expands those functions into code which extracts the virt proxy and then uses the appropriate method on it. This has two benefits. First, the Copy* functions where mostly redundant wrappers around the methods the proxy port already had. Second, using them forced a particular port which might not actually be what the user wanted. Change-Id: I62084631dd080061e3c74997125164f40da2d77c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18575 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-29sim-se: const for loader's loadSection paramBrandon Potter
The port proxy can be declared as a reference to a const proxy rather than just a reference to a proxy. Change-Id: I4640b0c5f33e2334c1e7630131f78607ced40a34 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12301 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-29cpu: Added correct return type for ROB::countInstsAndrea Mondelli
- return size_t (unsigned) according to the .size() return type - fixed typo in doc (source of warning with some compilers) Change-Id: I48ee2e317cf41011a6fcb5ca45aef67e75329bfa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18948 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-29mem-cache: Accuracy-based rate control for prefetchersJavier Bueno
Added a mechanism to control the number of prefetches generated based in the effectiveness of the prefetches generated so far. Change-Id: I33af82546f74a5b5ab372c28574b76dd9a1bd46a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18808 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-29sim-se: add a release parameter to Process.pyCiro Santilli
Set the default release to that single value for all ISAs. glibc has checks for the kernel version based on uname, and refuses to start any syscall emulation programs if those checks don't pass with error: FATAL: kernel too old The ideal solution to this problem is to actually implement all missing system calls for the required kernel version and bumping the release accordingly. However, it is very hard to implement all missing syscalls and verify compliance. Previously, we have simply bumped the version manually from time to time when major glibc versions started breaking. This commit alleviates the problem in two ways. Firstly, having a single kernel version for all versions means that it is easier to bump all versions at once. Secondly, it makes it is possible to set the release with a parameter, which in turn can be set from the command line with: se.py --param 'system.cpu[:].workload[:].release = "4.18.0"' Change-Id: I9e3c31073bfe68735f7b0775c8e299aa62b98222 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17849 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-29mem-cache: Support for page crossing prefetchesJavier Bueno
Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14620 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-29mem: Add a readString method to the PortProxy which takes a char *.Gabe Black
This version takes a char * instead of an std::string &, and a maximum length to fill in like strncpy. This is intended to be a replacement for the CopyStringOut function. Change-Id: Ib661924a3fa7e05761d572ffecbe2c0cc8659d48 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18574 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-29mem: Use a const T & in write<> to avoid an unnecessary copy.Gabe Black
If the type T is complex/large, the it makes sense to access it in place and not copy it and then not modify it. Change-Id: Idd24be4fbba636375637ff72b1ba5ee32eb76215 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18573 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-29mem, arm: Replace the pointer type in PortProxy with void *.Gabe Black
The void * type is for pointers which point to an unknown type. We should use that when handling anonymous buffers in the PortProxy functions, instead of uint8_t * which points to bytes. Importantly, C/C++ doesn't require you to do any casting to turn an arbitrary pointer type into a void *. This will get rid of lots of tedious, verbose casting throughout the code base. Change-Id: Id1adecc283c866d8e24524efd64f37b079088bd9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18571 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-29mem, arm: Move some helper methods into the base PortProxy class.Gabe Black
These were originally in the SETranslatingPortProxy class, but they're not specific to SE mode in any way and are an unnecessary divergence between the SE and FS mode translating port proxies. Change-Id: I8cb77531cc287bd15b2386410ffa7b43cdfa67d0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18570 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-29arm, mem: Move the SecurePortProxy subclass into it's own file.Gabe Black
The idea of a "secure" memory area/access is specific to ARM and shouldn't be in the common mem directory, although it's built in to the generic memory protocol at this point. Regardless, it should minimially be in its own file like the virtual and physical port proxy classes are. Change-Id: I140d4566ee2deded784adb04bcf6f11755a85c0c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18569 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-28mem: Parameterize coherent xbar sanity checksTiago Muck
Parameters can be used to change coherent xbar limits for the routing table and outstanding snoops. We need the ability to tweak these values as the current defaults may be violated in simulations with large core counts. Change-Id: Idb64b8c105683d02d8beba5bce13b815181ba824 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18789 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-28mem: Snoop filter support for large systemsTiago Muck
Changed SnoopMask to use std::bitset instead of uint64 so we can simulate larger systems without having to workaround limitations on the number of ports. No noticeable performance drop was observed after this change. The size of the bitset is currently set to 256 which should fit most needs. Change-Id: I216882300500e2dcb789889756e73a1033271621 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18791 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-28base: Add warn_if_once macroTiago Muck
Change-Id: Ie68f3b07a35ed2e6b0eee20b3b34050542fcdc6c Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18420 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-28cpu: Remove assert causing issues with x86 Linux bootGiacomo Gabrielli
Change-Id: I5e0b189ced0dd59ac6dbbb2c498c068e132b9b93 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18910 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-23 14:36:27 +0000