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2006-10-31remove connectAll() and connect() code since it isn't used anymore. (The ↵Ali Saidi
python does it all) --HG-- extra : convert_revision : e16a1ff59d4522703b155c2e68379a3072e8f47f
2006-10-31add the ability to insert into the middle of the timing port send listAli Saidi
--HG-- extra : convert_revision : 5422025f74ba7013f98d1d1dcbd1070f580aae61
2006-10-29An attempt to serialize the state of the micro code mechanism in the simple cpu.Gabe Black
src/cpu/simple/base.cc: Make a microcoded op start at the current micropc, rather than starting at 0. src/cpu/thread_state.cc: Serialize the microPC and nextMicroPC --HG-- extra : convert_revision : 5302215f17312ecef3ff4c6548acb05297ee4ff6
2006-10-29Move the mem classes into util.isa so that multiple inheritance can be used ↵Gabe Black
in the future for micro insts. --HG-- extra : convert_revision : c71faa5e43b56ed15d00ed5fd57c020d1c845445
2006-10-29Fix when the IsDelayedCommit flag is set.Gabe Black
--HG-- extra : convert_revision : ab6cd69f82b2013d66a91beaa3e39d8f417a9251
2006-10-29Bring casa and casxa up to dateGabe Black
src/arch/sparc/isa/decoder.isa: Fix up the casa and casxa instructions. src/arch/sparc/isa/formats/formats.isa: This is handled in loadstore.isa now src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version. src/arch/sparc/isa/formats/mem/mem.isa: The cas format is handled in loadstore.isa as well now. src/arch/sparc/isa/formats/mem/util.isa: Reorganized things a bit to better support cas --HG-- extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
2006-10-29Fixed ldstub to use the right format, and made the load/store operations use ↵Gabe Black
the integer microcode register. --HG-- extra : convert_revision : 7df5bd4bbe8a2607c7d2b4799826831d6a440926
2006-10-29Add an integer microcode register.Gabe Black
--HG-- extra : convert_revision : f23dbfdfe44e8e6cdd6948000669ad4f743b9fb4
2006-10-28Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : df73fd850d6638cbce6ff31203857f51235b8763
2006-10-28remove intel nic from SConscriptAli Saidi
--HG-- extra : convert_revision : b01bb258c97cf42d46a94faedab31726623fe437
2006-10-28This one really needs to be arch/faults.hhGabe Black
--HG-- extra : convert_revision : aad1ee04ade9f4394c9ef0386f23d6f2ca373412
2006-10-28Include the right version of faults.hhGabe Black
--HG-- extra : convert_revision : 4762b8ab46ac755726cc658a378c2cf5b2061dc3
2006-10-28Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : 9883fb35fd9c36e1819153f9976f8bdc73dbe8f3
2006-10-28One last adjustment to get rid of skew in the simple atomic cpu.Gabe Black
--HG-- extra : convert_revision : 8e46929ed7da5dae6888f773de4e1ecc9b249fe0
2006-10-27add packet_access.hhAli Saidi
--HG-- extra : convert_revision : 7fe4958549101fca9613baa4a317d96f4970d432
2006-10-27A more complete attempt to fix the clock skew.Gabe Black
--HG-- extra : convert_revision : b2d505de51fc5fcae5177b2a13140729474e249e
2006-10-27Potential fix to clock skew problem.Gabe Black
--HG-- extra : convert_revision : 51572523190a886fd0ff64817edc88e260c5fa9d
2006-10-27Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : ec35a9276ae21e0b9fe820bd700c020e4440a350
2006-10-27Got rid of some outdated comments.Gabe Black
--HG-- extra : convert_revision : 30fa768c4a934cf5f9dc0ad84e0e421327ccbed3
2006-10-27Made the regfile compatible with the new definitions in MiscRegFileGabe Black
--HG-- extra : convert_revision : d63ea6fb1e549e737204ee6653c06f89ec5e43ef
2006-10-27Clean up MiscRegFileGabe Black
--HG-- extra : convert_revision : 3bc792596c99df3a5c2c82da58b801a63ccf6ddb
2006-10-26Reorganized the MiscRegFileGabe Black
--HG-- extra : convert_revision : 088112c9b8a4ea09c8015da5a0b65ed2fc9398d2
2006-10-26Cleaned up the decoder slightly.Gabe Black
--HG-- extra : convert_revision : a7050aa8768c132f0161f00ba17ae02d71f0b829
2006-10-26Added a few functions to stuff values into bitfields in an instruction.Gabe Black
--HG-- extra : convert_revision : 507d7e13fd6276acf36b75eba31dff5e8080113f
2006-10-26Changed the number of register windows to be more realistic.Gabe Black
--HG-- extra : convert_revision : ae557307f377b19bae82226dafa8b4b2654cae52
2006-10-26Got rid of some debug outputGabe Black
--HG-- extra : convert_revision : 6e98cf839dc92bde5f06f9b9bf11ca6ac661c907
2006-10-26Change the default function from setMiscRegWithEffect to setMiscRegGabe Black
--HG-- extra : convert_revision : bedf422d51a52b009390b1e94f5330f752be2b87
2006-10-26Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : 473901bcd44bd2c563a3293d7326cd5aed8b630f
2006-10-25Fix simple timing port keep a list of all packets, have only one event, and ↵Ali Saidi
scan all packets on a functional access. --HG-- extra : convert_revision : c735a6408443b5cc90d1c1841c7aeb61e02ec6ae
2006-10-25Fixed the priv instruction format.Gabe Black
src/arch/sparc/isa/formats/priv.isa: Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated. src/arch/sparc/isa/operands.isa: Added an Hpstate operand, and adjusted the numbering. --HG-- extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
2006-10-25Implemented the saved and restored instructions, fixed up register window ↵Gabe Black
instructions so that the cwp is modified at the correct time (when handling the fault), and fixed the "done" instruction. --HG-- extra : convert_revision : 3c9144422f087af1d375782cce1c9b77ca7936c9
2006-10-25Fixed the bitfield FCN to include the right bits.Gabe Black
--HG-- extra : convert_revision : 040beb4dd982784773c3c3ad04cc48c2dc98b58c
2006-10-25Implemented the SPARC fill and spill handlers.Gabe Black
src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE src/arch/sparc/process.cc: src/arch/sparc/process.hh: Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart. --HG-- extra : convert_revision : 59adb96570cce86f373fbc2c3e4c05abe1742d3b
2006-10-25Fix fixPacket functionality to calculate sizes properlyRon Dreslinski
src/mem/packet.cc: Copy size is calculated by END-BEGIN not BEGIN-END --HG-- extra : convert_revision : 0e2725c5551f8f70ff05cb285e0822afc0bb3f87
2006-10-24Replace the Alpha No op with a SPARC one.Gabe Black
--HG-- extra : convert_revision : bed03e63dc80bf24f21bad08e6553d7aab92c7b3
2006-10-24Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : 4db140e6e8408b3ed39da327515b8e88a2701e6b
2006-10-24Add more traceflags for ethernetAli Saidi
--HG-- extra : convert_revision : a5025f501d72626d1bcb4dcc24ee353ceb160ce7
2006-10-24Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head --HG-- extra : convert_revision : a077304e608753f50f4a12216901d156469eebe4
2006-10-23Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem --HG-- extra : convert_revision : bb58679e101570d50c040519fb08ffbabfee7416
2006-10-23get rid of the "resume" step at the end of changeToTiming/Atomic because ↵Lisa Hsu
this will cause an assertion when you do the CPU switch. instead, push the responsibility of the resume upwards towards the user - documented in se.py and fs.py so it should be ok. --HG-- extra : convert_revision : 7530cf140844e18cc26df80057f8760f29ec952b
2006-10-23make this parallel to the other cpu types so that resume works correctly.Lisa Hsu
--HG-- extra : convert_revision : 3c165af27ea0e6c7f2a17819c1717d8900f54cc1
2006-10-23Minor compile fix. Not sure why this is broken.Gabe Black
--HG-- extra : convert_revision : 6f181b15f37114ca0a3965cabcb2036bd2f97916
2006-10-23Move around more SPARC memory code, and make block memory operations work ↵Gabe Black
with the timing cpu --HG-- extra : convert_revision : 37358504c4d05d78d08c19ba3d0c99d38c4babf5
2006-10-23Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : cb15101d24ef2969e1819d6bdeeb2dd1f23f02d1
2006-10-23Broke Load/Store instructions into microcode, and partially refactored ↵Gabe Black
memory operations in the SPARC ISA description. --HG-- rename : src/arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats/formats.isa rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/basicmem.isa rename : src/arch/sparc/isa/formats/blockmem.isa => src/arch/sparc/isa/formats/mem/blockmem.isa rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/mem.isa extra : convert_revision : dbbb00f997a102871b084b209b9fa08c5e1853ee
2006-10-23Don't let interupts interupt microcode at undesired points.Gabe Black
--HG-- extra : convert_revision : a8ddc6b213b1a1b0d9c5cd194b88ac0c6bfb2a21
2006-10-23Files in base shouldn't depend on things in sim. Changed "sim/host.hh" to ↵Gabe Black
<inttypes.hh> --HG-- extra : convert_revision : c1e46c012a26cdb0603416f8e8a99e0ecb1c09bc
2006-10-23Start making memory ops work with InitiateAcc and CompleteAcc, and some ↵Gabe Black
minor cleanups --HG-- extra : convert_revision : 178a8c5d0506c75ad7a7e8d691c8863235ed7e95
2006-10-23Change the default constructors to take ExtMachInsts rather than regular ↵Gabe Black
MachInsts --HG-- extra : convert_revision : 8fa34f82e0cbf5ce81775d572b182826c578581f
2006-10-22Clean up cache DPRINTFsSteve Reinhardt
--HG-- extra : convert_revision : f836e77efd40e25259d7794dd148696586b79a09
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