gem5 - gem5

Age	Commit message (Expand)	Author
2019-11-14	tests, base: Removed ambiguity from base/intmath.hh	Mahyar Samani
2019-11-14	arch-arm: Refactor code to check if gic is GicV2	Chun-Chen TK Hsu
2019-11-14	config: Add fastmodel cluster in fs_bigLITTLE.py	Chun-Chen TK Hsu
2019-11-14	fastmodel: Add VExpressFastmodel platform	Chun-Chen TK Hsu
2019-11-13	arm: Replace most htog and gtoh with htole and letoh.	Gabe Black
2019-11-13	arch-arm: fix routeToHyp for AArch64 in faults	Adrian Herrera
2019-11-13	tests: Added GTests for base/chunk_generator.hh	Bobby R. Bruce
2019-11-13	fastmodel: Implement reading vector registers with readVecReg.	Gabe Black
2019-11-13	tests: Added GTests for base/types.cc	Bobby R. Bruce
2019-11-12	tests,base: Added GTests for base/condcodes.hh	Bobby R. Bruce
2019-11-11	arch-arm: Fix TarmacParser handling of 64bit LD/ST	Giacomo Travaglini
2019-11-11	arch-arm: Provide SVE support to the TarmacTracer	Giacomo Travaglini
2019-11-11	arch-arm: Provide SVE support to the TarmacParser	Giacomo Gabrielli
2019-11-07	arm: Set the number of FloatRegs to zero.	Gabe Black
2019-11-07	tests,base: Added GTests for base/match.cc	Bobby R. Bruce
2019-11-07	cpu: Fix a bug in getCurrentInstCount in the checker CPU.	Gabe Black
2019-11-07	power: Replace gtoh and htog with betoh and htobe.	Gabe Black
2019-11-07	x86: Replace htog and gtoh with htole and letoh.	Gabe Black
2019-11-07	mips: Replace gtoh and htog with letoh and htole.	Gabe Black
2019-11-07	sparc: Replace htog and gtoh with htobe and betoh.	Gabe Black
2019-11-07	systemc: Remove boost dependency caused by tlm	Hoa Nguyen
2019-11-07	fastmodel: Plumb the ITB and DTB through the IRIS thread context.	Gabe Black
2019-11-06	fastmodel: Implement inst count events in the IRIS thread contexts.	Gabe Black
2019-11-06	arch-arm: Simplify AMO code generation templates	Nikos Nikoleris
2019-11-06	cpu: Use std::array for registers in SimpleThread.	Gabe Black
2019-11-05	arch-arm: Annotate original address in CMOs	Giacomo Travaglini
2019-11-05	mem-ruby: Reset Ruby Sequencer Outstanding Requests stats	Polydoros Petrakis
2019-11-05	dev-arm: optional instantiation of GICv3 ITS	Adrian Herrera
2019-11-04	mem-cache: Modify compressor to appease newer compilers	Daniel R. Carvalho
2019-11-04	mem-cache: Implement a perfect compressor	Daniel R. Carvalho
2019-11-04	mem-cache: Make BDI a multi compressor	Daniel R. Carvalho
2019-11-04	mem-cache: Implement a multi compressor	Daniel R. Carvalho
2019-11-04	mem-cache: Implement BDI sub-compressors	Daniel R. Carvalho
2019-11-04	mem-cache: Implement a repeated values compressor	Daniel R. Carvalho
2019-11-04	mem-cache: Implement a zero compressor	Daniel R. Carvalho
2019-11-04	mem-cache: Implement FPC-D cache compression	Daniel R. Carvalho
2019-11-02	arch,cpu: Move endianness conversion of inst bytes into the ISA.	Gabe Black
2019-11-01	mem: Delete the packet accessors which use guest endianness.	Gabe Black
2019-11-01	arch-x86: Fix FLDCW_P and FNSTCW_P to use rip.	seanzw
2019-11-01	arch-arm: generic method for getting an ArmSystem	Adrian Herrera
2019-11-01	dev-arm: Add SMMUv3 to VExpress_GEM5_V*	Giacomo Travaglini
2019-10-31	fastmodel: Add CortexA76x[234] models.	Gabe Black
2019-10-31	fastmodel: Enable auto bridging and use it to simplify CortexA76x1.	Gabe Black
2019-10-31	fastmodel: Templatize the xn versions of the CortexA76.	Gabe Black
2019-10-31	mem-cache: Fix missing header in associative set	Daniel R. Carvalho
2019-10-31	mem-ruby: Fixed pipeline squashes caused by aliased requests	Joe Gross
2019-10-31	cpu-o3: bugfix for partial faults in x86	Brandon Potter
2019-10-31	alpha: Convert htog and gtoh to htole and letoh.	Gabe Black
2019-10-30	arch,sim: Make copyStringArray take an explicit endianness.	Gabe Black
2019-10-30	kern: When dumping dmesg, detect the byte order dynamically.	Gabe Black