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AgeCommit message (Collapse)Author
2011-02-11VNC/ARM: Use VNC server and add support to boot into X11Ali Saidi
2011-02-11VNC: Add VNC server to M5Ali Saidi
2011-02-11Serialization: Allow serialization of stl listsAli Saidi
2011-02-11O3: Fix pipeline restart when a table walk completes in the fetch stage.Giacomo Gabrielli
When a table walk is initiated by the fetch stage, the CPU can potentially move to the idle state and never wake up. The fetch stage must call cpu->wakeCPU() when a translation completes (in finishTranslation()).
2011-02-11O3: Fix a few bugs in the TableWalker object.Giacomo Gabrielli
Uncacheable requests were set as such only in atomic mode. currState->delayed is checked in place of currState->timing for resetting currState in atomic mode.
2011-02-11SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk ↵Ali Saidi
occurs. This change fixes an issue where a DTLB fault occurs and redirects fetch to handle the fault and the ITLB requires a walk which delays translation. In this case the status of the cpu isn't updated appropriately, and an additional instruction fetch occurs. Eventually this hits an assert as multiple instruction fetches are occuring in the system and when the second one returns the processor is in the wrong state. Some asserts below are removed because it was always true (typo) and the state after the initiateAcc() the processor could be in any valid state when a d-side fault occurs.
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs, when a TLB miss occurs, initiateTranslation() can return with NoFault but with the translation unfinished. Instructions experiencing a delayed translation due to a hardware page table walk are deferred until the translation completes and kept into the IQ. In order to keep track of them, the IQ has been augmented with a queue of the outstanding delayed memory instructions. When their translation completes, instructions are re-executed (only their initiateAccess() was already executed; their DTB translation is now skipped). The IEW stage has been modified to support such a 2-pass execution.
2011-02-11ARM: Fix timer calculations.Ali Saidi
The timer calculations were a bit off so time would run faster than it otherwise should
2011-02-11Timesync: Make sure timesync event is setup after curTick is unserializedAli Saidi
Setup initial timesync event in initState or loadState so that curTick has been updated to the new value, otherwise the event is scheduled in the past.
2011-02-09ruby: removed duplicate make response callBrad Beckmann
2011-02-08MESI CMP: Unset TBE pointer in L2 cache controllerNilay Vaish
The TBE pointer in the MESI CMP implementation was not being set to NULL when the TBE is deallocated. This resulted in segmentation fault on testing the protocol when the ProtocolTrace was switched on.
2011-02-07X86: Obey the wp bit of CR0.Tim Harris
If cr0.wp ("write protect" bit) is clear then do not generate page faults when writing to write-protected pages in kernel mode.
2011-02-07X86: Use all 64 bits of the lstar register in the SYSCALL_64 macroop.Tim Harris
During SYSCALL_64, use dataSize=8 when handling new rip (ref http://www.intel.com/Assets/PDF/manual/253668.pdf 5.8.8 IA32_LSTAR is a 64-bit address)
2011-02-07X86: Fix JMP_FAR_I to unpack a far pointer correctly.Tim Harris
JMP_FAR_I was unpacking its far pointer operand using sll instead of srl like it should, and also putting the components in the wrong registers for use by other microcode.
2011-02-07X86: Read the LDT/GDT at CPL0 when executing an iret.Tim Harris
During iret access LDT/GDT at CPL0 rather than after transition to user mode (if I'm reading the Intel IA-64 architecture spec correctly, the contents of the descriptor table are read before the CPL is updated).
2011-02-07Orion: Replace printf() with fatal()Nilay Vaish
The code for Orion 2.0 makes use of printf() at several places where there as an error in configuration of the model. These have been replaced with fatal().
2011-02-07ruby: add stdio header in SRAM.hhKorey Sewell
missing header file caused RUBY_FS to not compile
2011-02-07X86: Fix compiling vtophys.ccGabe Black
2011-02-06ruby: support to stallAndWait the mandatory queueBrad Beckmann
By stalling and waiting the mandatory queue instead of recycling it, one can ensure that no incoming messages are starved when the mandatory queue puts signficant of pressure on the L1 cache controller (i.e. the ruby memtester). --HG-- rename : src/mem/slicc/ast/WakeUpDependentsStatementAST.py => src/mem/slicc/ast/WakeUpAllDependentsStatementAST.py
2011-02-06ruby: minor fix to deadlock panic messageBrad Beckmann
2011-02-06garnet: Split network power in ruby.statsJoel Hestness
Split out dynamic and static power numbers for printing to ruby.stats
2011-02-06MOESI_hammer: fixed dir bug counting received acksBrad Beckmann
2011-02-06ruby: numa bit fix for sparse memoryBrad Beckmann
2011-02-06MOESI_CMP_token: removed unused message fieldsTushar Krishna
2011-02-06mem: Added support for Null data packetBrad Beckmann
The packet now identifies whether static or dynamic data has been allocated and is used by Ruby to determine whehter to copy the data pointer into the ruby request. Subsequently, Ruby can be told not to update phys memory when receiving packets.
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-06dev: fixed bugs to extend interrupt capability beyond 15 coresBrad Beckmann
2011-02-06x86: Timing support for pagetable walkerJoel Hestness
Move page table walker state to its own object type, and make the walker instantiate state for each outstanding walk. By storing the states in a queue, the walker is able to handle multiple outstanding timing requests. Note that functional walks use separate state elements.
2011-02-06TimingSimpleCPU: split data sender state fixJoel Hestness
In sendSplitData, keep a pointer to the senderState that may be updated after the call to handle*Packet. This way, if the receiver updates the packet senderState, it can still be accessed in sendSplitData.
2011-02-06ruby: Fix RubyPort to properly handle retrysBrad Beckmann
2011-02-06Ruby: Fix to return cache block size to CPU for split data transfersJoel Hestness
2011-02-06Ruby: Add support for locked memory accesses in X86_FSJoel Hestness
2011-02-06Ruby: Update the Ruby request type names for LL/SCJoel Hestness
2011-02-06ruby: Assert for x86 misaligned accessBrad Beckmann
This patch ensures only aligned access are passed to ruby and includes a fix to the DPRINTF address print.
2011-02-06MOESI_hammer: Added full-bit directory supportBrad Beckmann
2011-02-06x86: Add checkpointing capability to devicesJoel Hestness
Add checkpointing capability to the Intel 8254 timer, CMOS, I8042, PS2 Keyboard and Mouse, I82094AA, I8237, I8254, I8259, and speaker devices
2011-02-06x86: Add checkpointing capability to arch componentsJoel Hestness
Add checkpointing capability to the x86 interrupt device and the TLBs
2011-02-06x86: implements vtophysJoel Hestness
Calls walker to look up virt. to phys. page mapping
2011-02-06IntDev: packet latency fixJoel Hestness
The x86 local apic now includes a separate latency parameter for interrupts.
2011-02-06MessagePort: implement the virtual recvTiming function to avoid double pkt ↵Joel Hestness
delete Double packet delete problem is due to an interrupt device deleting a packet that the SimpleTimingPort also deletes. Since MessagePort descends from SimpleTimingPort, simply reimplement the failing code from SimpleTimingPort: recvTiming.
2011-02-06MOESI_hammer: trigge queue fix.Joel Hestness
2011-02-06mcpat: Adds McPAT performance countersJoel Hestness
Updated patches from Rick Strong's set that modify performance counters for McPAT
2011-02-06garnet: added orion2.0 for network power calculationTushar Krishna
2011-02-06garnet: separate data and ctrl VCsTushar Krishna
Separate data VCs and ctrl VCs in garnet, as ctrl VCs have 1 buffer per VC, while data VCs have > 1 buffers per VC. This is for correct power estimations.
2011-02-06x86: set IsCondControl flag for the appropriate microopsBrad Beckmann
2011-02-03Fault: Forgot to refresh to grab these header guard updates.Gabe Black
2011-02-04inorder: fault handlingKorey Sewell
Maintain all information about an instruction's fault in the DynInst object rather than any cpu-request object. Also, if there is a fault during the execution stage then just save the fault inside the instruction and trap once the instruction tries to graduate
2011-02-04inorder: pcstate and delay slots bugKorey Sewell
not taken delay slots were not being advanced correctly to pc+8, so for those ISAs we 'advance()' the pcstate one more time for the desired effect
2011-02-04inorder: add a fetch buffer to fetch unitKorey Sewell
Give fetch unit it's own parameterizable fetch buffer to read from. Very inefficient (architecturally and in simulation) to continually fetch at the granularity of the wordsize. As expected, the number of fetch memory requests drops dramatically
2011-02-04inorder: overload find-req fnKorey Sewell
no need to have separate function name findSplitRequest, just overload the function