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2017-12-06base: Handle zero fill in cprintf when printing floats.Gabe Black
The fill_zero flag was being followed for ints, but not for floats. This makes the cprintf unit test pass. Change-Id: I4d17a3c9327aea05e0a3c81be1886c0c9256f03c Reviewed-on: https://gem5-review.googlesource.com/6322 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-06tests: Fix the source file for the cprintftime test.Gabe Black
It was using the source file for the cprintftest unit test. Change-Id: I534798e892ad55cef2f48be2ba9d732aa1993819 Reviewed-on: https://gem5-review.googlesource.com/6321 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-06scons: Several fixes having to do with tags and sets.Gabe Black
There were a few places where tags weren't being converted to sets correctly which unfortunately only manifested when called in certain ways. This would be a pretty reasonable place to add some python unit tests... Change-Id: I87509369b4ec6f702b7521e52bf63701a87ec436 Reviewed-on: https://gem5-review.googlesource.com/6261 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-06scons: Track and reuse object nodes for a given source file.Gabe Black
scons gets upset if two different environments are used to set up a particular object file. This change adds two dicts to the SourceFile class, one for static and one for shared object files, which are keyed off of the appropriate suffix. If a suffix hasn't been set up yet, a new node of the appropriate type is set up and stored in the cache, and then whatever is in the cache (new or old) is returned. Change-Id: Ice4b4fc728b438a4d3316c3ff6667c0480d2a6d7 Reviewed-on: https://gem5-review.googlesource.com/6224 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-05x86: LOOP's operand size defaults to 64 bits in 64 bit mode.Gabe Black
The microcode for those instructions needs a directive which overrides that setting in the instructions emulation environment. Reported-by: Matt Sinclair <mattdsinclair@gmail.com> Change-Id: I474d938c0b3cf01da92ec817a58b08de783f1967 Reviewed-on: https://gem5-review.googlesource.com/6301 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-05learning-gem5: Fix missing misc.hh in hello_object.ccHanhwi Jang
misc.hh has been renamed in commit 1088f0c4ac3999fc3c363cc51daef4cfb360a2bd Change-Id: Ic4f8c6423e6a5466f8d924e793a24f62bb4eca9c Reviewed-on: https://gem5-review.googlesource.com/6361 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-12-05arm: Add support for the dc {civac, cvac, cvau, ivac} instrNikos Nikoleris
This patch adds support for decoding and executing the following ARMv8 cache maintenance instructions by Virtual Address: * dc civac: Clean and Invalidate by Virtual Address to the Point of Coherency * dc cvac: Clean by Virtual Address to the Point of Coherency * dc cvau: Clean by Virtual Address to the Point of Unification * dc ivac: Invalidate by Virtual Addrsess to the Point of Coherency Change-Id: I58cabda37f9636105fda1b1e84a0a04965fb5670 Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5060 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-05arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructionsNikos Nikoleris
This patch adds support for the ARMv7 cache maintenance intructions: * mcr dccmvac cleans a VA to the PoC * mcr dcimvac invalidates a VA to the PoC * mcr dccimvac cleans and invalidates a VA to the PoC * mcr dccmvau cleans a VA to the PoU Change-Id: I6511f203039ca145cc9128ddf61d09d6d7e40c10 Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5059 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem-ruby: Prevent ruby from crashing on CMOsNikos Nikoleris
Ruby has no support for cache maintenace operations. As a workaround, after printing a warning, we treat them as no-ops in the memory system and respond immediately without handling them. There should be workarounds in the memory system already that allow execution to proceed without the requirement for cache maintenance operations. Change-Id: I125ee4fa37b674c636d87f2d9205bbc1a74da101 Reviewed-on: https://gem5-review.googlesource.com/5057 Reviewed-by: Jieming Yin <bjm419@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-12-05arm: Add CMO support for Non-Cacheable memoryNikos Nikoleris
Cache Maintainance operations to the point of coherence are treated as normal cahceable requests and clean and/or invalidate the caches of all PEs. Change-Id: Ia4a749c2318fe29c8601848b034b8315c4186c8a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5056 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05cpu: Add support for CMOs in the cpu modelsNikos Nikoleris
Cache maintenance operations go through the write channel of the cpu. This changes makes sure that the cpu does not try to fill in the packet with data. Change-Id: Ic83205bb1cda7967636d88f15adcb475eb38d158 Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5055 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Ignore clean requests in the abstract memoryNikos Nikoleris
Systems with atomic cores and the fastmem option enabled bypass the whole memory system and access the abstract memory directly. Cache maintenance operations which would be normally handled before the point of unification/coherence should be ignored by the abstract memory. Change-Id: I696cdd158222e5fd67f670cddbcf2efbbfd5eca4 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5054 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Handle CMO responses in the snoop filterNikos Nikoleris
Previously responses would either transfer the ownership of the line or the actual data to the cache that send out the original request. Cache clean operations are different since they bring neither data nor ownership. When they are also invalidating the cache that send out the original request will invalidate any existing copies. This patch makes the snoop filter handle the cache clean responses accordingly. Change-Id: I27165cb45b9dc57882526329c62db35f100d23df Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5053 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Allow CMOs as snooping requests in the snoop filterNikos Nikoleris
The snoop filter performs sanity checks of the type of packets that are expected to snoop caches above. Cache maintenace operations are expected to perform a clean and or invalidate on all caches down to the specified point of reference and therefore could also generate snoops. Change-Id: I7f8fef246a85faa87ccd289c28b49686ed7caa08 Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5052 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Co-ordination of CMOs in the xbarNikos Nikoleris
A clean packet request serving a cache maintenance operation (CMO) visits all memories down to the specified xbar. The visited caches invalidate their copy (if the CMO is invalidating) and if a dirty copy is found a write packet writes the dirty data to the memory level below the specified xbar. A response is send back when all the caches are clean and/or invalidated and the specified xbar has seen the write packet. This patch adds the following functionality in the xbar: 1) Accounts for the cache clean requests that go through the xbar 2) Generates the cache clean response when both the cache clean request and the corresponding writeclean packet has crossed the destination xbar. Previously transactions in the xbar were identified using the pointer of the original request. Cache clean transactions comprise of two different packets, the clean request and the writeclean, and therefore have different request pointers. This patch adds support for custom transaction IDs that by default take the value of the request pointer but can be overriden by the contructor. This allows the clean request and writeclean share the same id which the coherent xbar uses to co-ordinate them and send the response in a timely manner. Change-Id: I80db76386a1caded38dc66e6e18f930c3bb800ff Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5051 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Add support for handling CMOs in the MSHRsNikos Nikoleris
To add support for cache maintenance operations (CMOs) in the MSHRs, this change adds the following functionality: - If a CMO request hits in the MSHRs, we deferred as we can't coalesce it with any other requests. - When we promote any deferred targets, we promote them in order and stop if we encounter a CMO request. If the CMO request is at the beginning of the deferred targets list it will be the only promoted target. Change-Id: I10d1f7e16bd6d522d917279c5d408a3f0cee4286 Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5050 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Add support for CMOs in the cacheNikos Nikoleris
This change adds support for maintenance operations (CMOs) in the cache. The supported memory operations clean and/or invalidate a cache block as specified by its VA to the specified xbar (PoU, PoC). A cache maintenance packet visits all memories down to the specified xbar. Caches need to invalidate their copy if it is an invalidating CMO. If it is (additionally) a cleaning CMO and a dirty copy exists, the cache cleans it with a WriteClean request. Change-Id: Ibf31daa7213925898f3408738b11b1dd76c90b79 Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5049 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Promote deferred targets only when the block is validNikos Nikoleris
When a response indicates that there are no other sharers of the block, the cache can promote its copy of the block to writable and potential service deferred targets even if the request didn't ask for a writable copy. Previously, a response would guarantee the presence of the block in the cache. A response could either be filling, upgrading or a response to an invalidation due to a pending whole line write. Responses to cache maintenance invalidations break this assumption. This change adds an extra check to make sure that the block was already valid or that the response is filling before promoting the block. Change-Id: I6839f683a05d4dad4205c23f365a925b7b05e366 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5048 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Add support for cache maintenance operation requestsNikos Nikoleris
This change adds new packet cmds and request flags for cache maintenance operations. 1) A cache clean operation writes dirty data in the first memory below the specified xbar and updates any old copies in the memories above it. 2) A cache invalidate operation invalidates all copies of the specified block in the memories above the specified xbar 3) A clean and invalidate operation is a combination of the two operations above Change-Id: If45702848bdd568de532cd57cba58499e5e4354c Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5047 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Support for specifying the destination of a WriteCleanNikos Nikoleris
Previously, WriteClean packets would always write to the first memory below unless the memory was unable to allocate in which case it would be forwarded further below. This change adds support for specifying the destination of a WriteClean packet. The cache annotates the request with the specified destination and marks the packet as write-through upon its creation. The coherent xbar checks packets for their destination and resets the write-through flag when necessary e.g., the coherent xbar that is set as the PoC will reset the write-through flag for packets to the PoC. Change-Id: I84b653f5cb6e46e97e09508649a3725d72d94606 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5046 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Add support for WriteClean packets in the memory systemNikos Nikoleris
This change adds support for creating and handling WriteClean packets. The WriteClean operation is almost identical to a WritebackDirty with the exception that the cache generating a WriteClean retains a copy of the block. Change-Id: I63c8de62919fad0f9547d412f8266aa4292ebecd Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5045 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-05mem: Add a WriteClean command to the packet classNikos Nikoleris
A WriteClean packet allows a cache to write a block to a memory below without evicting its copy. A typical usecase for a WriteClean packet is a cache clean operation. Change-Id: If356cb067da5ddf3210c135f41ef0891fb811568 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5044 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem-cache: Add support for checking whether a cache is busyNikos Nikoleris
This changeset adds support for checking whether the cache is currently busy and a timing request would be rejected. Change-Id: I5e37b011b2387b1fa1c9e687b9be545f06ffb5f5 Reviewed-on: https://gem5-review.googlesource.com/5042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-05mem: Add function to check if the slave can receive a timing reqNikos Nikoleris
This changeset adds support for tryTiming, an interface that allows a master to check if the slave is busy or otherwise if it can accept a timing request. Change-Id: Idc7c2337ae9ccf5dec54f308e488660591419a63 Reviewed-on: https://gem5-review.googlesource.com/5041 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Christian Menard <christian.menard@tu-dresden.de> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Add the notion of point of unification in the coherent xbarNikos Nikoleris
The point of unification is the first crossbar at which the instruction cache, the data cache and the translation table walks of the core are guaranteed to see the same copy of a memory location. Change-Id: Ica79b34c8ed4f1a8f2379748e8520a8f8afffa90 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5040 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-05learning_gem5: Adding code for SimpleCacheJason Lowe-Power
This is the rest of the code for part 2. See http://learning.gem5.org/book/part2/simplecache.html Change-Id: I5db099266a1196914656be3858fdd5fb4f8eab48 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5023 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-05learning_gem5: Adds the simple MemObject codeJason Lowe-Power
Adding more code from Learning gem5 Part II See http://learning.gem5.org/book/part2/memoryobject.html Change-Id: Iaa9480c5cdbe4090364f02e81dc1d0a0ddac392a Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5022 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-05learning_gem5: Add code for hello-goodbye exampleJason Lowe-Power
Adding more code from Learning gem5 Part II See http://learning.gem5.org/book/part2/parameters.html Change-Id: I9fe5655239e011c718c5cf5fd62bebcda66ea966 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5021 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-05learning_gem5: Add code for simple SimObjectJason Lowe-Power
This adds code from Learning gem5 Part II. See http://learning.gem5.org/book/part2/helloobject.html Change-Id: Ic2caa07876ca57f937729c27ce29b2cd8bf2380c Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5020 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-04base: Rework the trie dump function to accept a different ostream.Gabe Black
It might often be useful to write output to cout when dumping a trie, but sometimes it might be useful to dump ot to something else like a string stream instead. Change-Id: Iaa4ae772c902b7dbc753f320d1a7eb5fcd4a3db3 Reviewed-on: https://gem5-review.googlesource.com/6266 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
These files aren't a collection of miscellaneous stuff, they're the definition of the Logger interface, and a few utility macros for calling into that interface (panic, warn, etc.). Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1 Reviewed-on: https://gem5-review.googlesource.com/6226 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-04misc: Move the ExitLogger class definition into misc.ccGabe Black
This class isn't referred to outside of misc.hh, and isn't necessarily useful outside of the particular logging setup implemented in misc.cc. The Logger class itself is different since it provides a generic interface that can be used with different logging schemes. Change-Id: Ibae926fea039d9e3d75a43d97348bc4a3c5d555e Reviewed-on: https://gem5-review.googlesource.com/6225 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-04tests: Remove trietest's dependence on cprintf.Gabe Black
Dumping the structure of the tries being constructed was useful for debugging when the trie data structure was being developed, but the output can't be automatically verified easily, and what's considered correct depends on the specific implementation of the trie itself. To make some of the earlier tests more meaningful, additional lookups were added which verified that the correct values were returned when the nodes of the trie were in particular arrangements. Change-Id: Ib464ad1804d13fe40882da2190d7bf452da83818 Reviewed-on: https://gem5-review.googlesource.com/6223 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-04tests: Add a ptr helper function trietest.Gabe Black
This function casts an integer constant into a uint32_t * to make the actual test lines a bit less verbose. Change-Id: I9307dfd3d5861ddb9c0f6dcf4b28c846004f0a8d Reviewed-on: https://gem5-review.googlesource.com/6222 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-04tests: Get rid of the bitvectest unit test.Gabe Black
This test doesn't really test anything other than the STL vector implementation. Change-Id: I1b932640b1be4fb92a44d314d0b51a94a6a324a2 Reviewed-on: https://gem5-review.googlesource.com/6221 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-01arm: Enable ns registers access in secure modeGiacomo Travaglini
Arm security extension introduced register banking between secure and non-secure mode. This has been removed in armv8 using AArch64 in EL3, where the decoded register is by default the non-secure version. Using non-secure register infos(flags) was preventing secure execution to access the register with the MRC/MCR at EL1. The patch updates the following banked registers' flags so that their non-secure version can be accessed in secure mode: MISCREG_CSSELR, MISCREG_SCTLR, MISCREG_ACTLR, MISCREG_TTBR0, MISCREG_TTBR1, MISCREG_TTBCR, MISCREG_DACR, MISCREG_DFSR, MISCREG_IFSR, MISCREG_ADFSR, MISCREG_AIFSR, MISCREG_DFAR, MISCREG_IFAR, MISCREG_PAR, MISCREG_PRRR, MISCREG_MAIR0, MISCREG_NMRR, MISCREG_MAIR1, MISCREG_AMAIR0, MISCREG_AMAIR1, MISCREG_VBAR, MISCREG_CONTEXTIDR, MISCREG_TPIDRURW, MISCREG_TPIDRURO, MISCREG_TPIDRPRW, MISCREG_CNTP_TVAL, MISCREG_CNTP_CTL, MISCREG_CNTP_CVAL For those registers the following permission bits have been set: MISCREG_PRI_S_RD MISCREG_PRI_S_WR Change-Id: Ib881c526e75d69e313f8ef66eb78fc704de6bf59 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6201 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-30arch-riscv: use sext rather than manual masksAlec Roelke
Replace manual creation of masks for sign extension of immediates with the sext<N> function. Change-Id: Ief2df91a25500c64f5bcae0dcd437c1e3bb95e6c Reviewed-on: https://gem5-review.googlesource.com/6182 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-30arch-riscv: Remove spaces around ea_codeAlec Roelke
This patch makes mem.isa conform to style guidelines better by removing spaces around the "ea_code" argument default value assignment of the Load format. Change-Id: I1c62b99de3617a3734b128b00fb421773e021317 Reviewed-on: https://gem5-review.googlesource.com/6181 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29arch-riscv: Add missing license paragraphsAlec Roelke
Some of the files in earlier patches rearranging instruction definitions were missing copyright and license information. This patch adds them. Change-Id: I2ac4910a415de6032fc0b7d4422904c682e0ad87 Reviewed-on: https://gem5-review.googlesource.com/6183 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-11-29cpu: Don't override ISA if provided by userAndreas Sandberg
The BaseCPU.createThreads() method currently overrides the BaseCPU.isa parameter. This is sometimes undesirable. Change the behavior so that the default value for the isa parameter is the empty list and teach createThreads() to only override the ISA if none has been specified. Change-Id: I2ac5535e55fc57057e294d3c6a93088b33bf7b84 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6121 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-11-29cpu-minor: Add missing instruction statsDavid Guillen Fandos
Change-Id: I811b552989caf3601ac65a128dbee6b7bb405d7f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Updated to use IsVector instruction flag. ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5732 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-11-29arch-riscv: Remove static parts of AMOs out of ISAAlec Roelke
This patch removes the static parts of the RISC-V atomic memory instructions out of the ISA generated code and into arch/riscv/insts. It also makes the LR and SC instructions subclasses of MemInst from arch/riscv/insts/mem.hh. Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 Reviewed-on: https://gem5-review.googlesource.com/6025 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29arch-riscv: Move parts of mem insts out of ISAAlec Roelke
This patch moves static portions of the memory instructions out of the ISA generated code and puts them into arch/riscv/insts. It also simplifies the definitions of load and store instructions by giving them a common base class. Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803 Reviewed-on: https://gem5-review.googlesource.com/6024 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29arch-riscv: Move unknown out of ISA descriptionAlec Roelke
This patch removes the Unknown instruction type out of the ISA generated code and puts it into arch/riscv/insts. Since there isn't any dynamic behavior to it, all that's left behind is a template for creating a new Unknown instruction. Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db Reviewed-on: https://gem5-review.googlesource.com/6023 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29arch-riscv: Move standard ops out of ISAAlec Roelke
This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp<T>. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-28cpu-o3: Add missing vector stat initializersAndreas Sandberg
All of the O3 vector stats added by 'arch: ISA parser additions of vector registers' are currently missing their stat initializers. Add the missing stat initialization to InstructionQueue::regStats. Change-Id: Idc4b8e2824120a2542d8a604340a1b41bde6aa28 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6101 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-11-28arch-arm: Add haveEL pseudocode functionGiacomo Travaglini
This patch introduces the ARM pseudocode haveEL function into gem5. Change-Id: I0d96070959e8e13773eb7fa9964894ec0ff2cac2 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6162 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-28arch-arm: Add assertions when extracting an ArmSystem from a TCGiacomo Travaglini
We sometimes need to cast the System pointer stored in a ThreadContext to an ArmSystem pointer to query global system setting. Add an assertion to make sure that the cast resulted in a valid pointer. Change-Id: Id382d0c1dceefee8f74d070c205c7b43b83ab215 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6161 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-28tests: Move the bituniontest to be alongside the bitunion header.Gabe Black
Change-Id: I7c1a49c41672a1108fcf67c5505b0441f90588ef Reviewed-on: https://gem5-review.googlesource.com/6142 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-28scons: Build GTests in the directory they're declared.Gabe Black
This will let us move unit tests into the directory of the code they're testing. Change-Id: I611582eb00a06a848f3ce7da89f64e42660cb844 Reviewed-on: https://gem5-review.googlesource.com/6141 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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