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AgeCommit message (Expand)Author
2018-07-17dev, arm: accept and ignore writes to GIC APRn registersCiro Santilli
2018-07-16systemc: Add a stub kernel SimObject.Gabe Black
2018-07-16systemc: Add a stubbed out sc_object class.Gabe Black
2018-07-16arch-arm: Introduce ARMv8.1 Virtual Timer System RegistersGiacomo Travaglini
2018-07-16arch-arm: Introduce RAS System RegistersGiacomo Travaglini
2018-07-13cpu: Add a Python-enabled traffic generatorAndreas Sandberg
2018-07-13cpu: Support trace termination in BaseTrafficGenAndreas Sandberg
2018-07-13cpu: Unify error handling for address generatorsAndreas Sandberg
2018-07-13cpu: Split the traffic generator into two classesAndreas Sandberg
2018-07-10misc: Fix BaseCPU doxygenJason Lowe-Power
2018-07-09arch-riscv: enable rudimentary fs simulationRobert
2018-07-09arch-riscv: Fix the srlw and srliw instructions.Austin Harris
2018-06-29base: Add a M5_PUBLIC and M5_LOCAL attribute macroAndreas Sandberg
2018-06-28python: Fix call bug in @cxxMethod when override is TrueAndreas Sandberg
2018-06-28cpu: Remove reduntant protobuf includesAndreas Sandberg
2018-06-28python: Fixup incorrect syntax in PyBind argument handlerAndreas Sandberg
2018-06-28mem: Add a memory delay simulatorAndreas Sandberg
2018-06-28arch-arm: Fix incorrect t{0,1}sz field in TTBCRAndreas Sandberg
2018-06-28base: Add an asymmetrical Coroutine classGiacomo Travaglini
2018-06-26gpu-compute: Remove unneeded Request::setVirt callAlexandru Dutu
2018-06-26python: Add support for multiplying proxies to compatible ParamNikos Nikoleris
2018-06-26scons: Generalize building binaries.Gabe Black
2018-06-25syscall_emul: adding symlink system callMatt Sinclair
2018-06-25syscall_emul: adding link system callMatt Sinclair
2018-06-22mem-cache: Promote deferred targets on cache clean responsesNikos Nikoleris
2018-06-22mem-cache: Promote targets that don't require writableNikos Nikoleris
2018-06-22mem-cache: Fix promoting of targets that need writableNikos Nikoleris
2018-06-22mem-cache: Selectively clear downstream pendingNikos Nikoleris
2018-06-22arch-arm: AArch32 execution triggering AArch64 SW BreakGiacomo Travaglini
2018-06-22arch-arm: BadMode checking if corresponding EL is implementedGiacomo Travaglini
2018-06-21base: Add a class which encapsulates Fibers.Gabe Black
2018-06-21sim: Use the canonical way of iterating over a dictionaryAndreas Sandberg
2018-06-21dev-arm: Use recurseDeviceTree instead of custom in platformAndreas Sandberg
2018-06-21cpu: Fix bug introduced by RequestPtr type changeGiacomo Travaglini
2018-06-20base: Fix includes in AddrRangeMap header fileNikos Nikoleris
2018-06-20mem-cache: Fix TempCacheBlock insertJason Lowe-Power
2018-06-19mem: Use address range to find the right physical addressNikos Nikoleris
2018-06-19mem: Use address range to find the destination port in the xbarNikos Nikoleris
2018-06-19mem: Use the caching in the AddrRangeMap class in PhysicalMemoryGabe Black
2018-06-19mem: Use the caching built into AddrRangeMap in the xbarGabe Black
2018-06-19base: Build caching into the AddrRangeMap classGabe Black
2018-06-19base, mem: Disambiguate if an addr range is contained or overlapsNikos Nikoleris
2018-06-19mem-cache: Fix support for secure blocks in the FALRU cacheNikos Nikoleris
2018-06-15mem-cache: Initialize CacheBlk data pointerDaniel R. Carvalho
2018-06-15mem-cache: Forward declare ReplaceableEntryDaniel R. Carvalho
2018-06-15dev-arm: Fix the address range for some I/O devicesNikos Nikoleris
2018-06-15sim: Add a SimObject python field which overrides the default c++ base.Gabe Black
2018-06-14cpu: Prevent suspended TimingSimple CPUs from fetching next instructionsTuan Ta
2018-06-14cpu: add a new instruction type 'Atomic'Tuan Ta
2018-06-14arch: support issuing Atomic Mem Operation (AMO) requestsTuan Ta
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