summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2019-05-02dev-arm: Store a PhysProxy port in Gicv3RedistGiacomo Travaglini
2019-05-02dev-arm: Add named variable for GICD_TYPER.IDBitsGiacomo Travaglini
2019-05-02dev-arm: Read correct version of ICC_BPR registerGiacomo Travaglini
2019-05-02dev-arm: Get a Gicv3Redistributor ptr from phys addressGiacomo Travaglini
2019-05-02dev-arm: Add several LPI methods in Gicv3RedistributorGiacomo Travaglini
2019-05-02dev-arm: Take LPIs into account when interacting with CPUIF regsGiacomo Travaglini
2019-05-02dev-arm: Fix GICv3 LPIs priority valueGiacomo Travaglini
2019-05-02dev-arm: Disable LPI Configuration Table cachingGiacomo Travaglini
2019-05-02dev-arm: Check EnableLPIs before checking for pending LPIsGiacomo Travaglini
2019-05-02dev-arm: GICv3 LPI tables are using physical addressesGiacomo Travaglini
2019-05-02dev-arm: Fix GICv3 LPI loopGiacomo Travaglini
2019-05-02dev-arm: Fix Bitwise operation in GICv3Giacomo Travaglini
2019-04-30arch: Stop using TheISA within the ISAs.Gabe Black
2019-04-30x86: Get rid of some unnecessary TheISA-es in x86.Gabe Black
2019-04-30sparc: Move translation constants from isa_traits.hh into tlb.hh.Gabe Black
2019-04-30sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.Gabe Black
2019-04-30arch: Remove the mt.hh switching header.Gabe Black
2019-04-30cpu: alpha: Delete all occurrances of the simPalCheck function.Gabe Black
2019-04-30alpha: Implement simPalCheck within the ISA description.Gabe Black
2019-04-30cpu: Remove hwrei from the generic interfaces.Gabe Black
2019-04-30sim-se: use DPRINTF_SYSCALL for ioctl/wait4Alexandru Dutu
2019-04-30sim-se: bugfix for 54c77aa055eBrandon Potter
2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
2019-04-30alpha: Implement HWREI in the ISA.Gabe Black
2019-04-30alpha: Add some control registers to the ISA operands list.Gabe Black
2019-04-30sim-se: add socket ioctlsBrandon Potter
2019-04-30systemc: Add a distinct async_request_update mechanism.Gabe Black
2019-04-29cpu: Get rid of the (read|set)RegOtherThread methods.Gabe Black
2019-04-29mips: Implement readRegOtherThread and setRegOtherThread directly.Gabe Black
2019-04-29cpu: Include debug flags regardless of whether the ISA is null.Gabe Black
2019-04-29sim-se: create Proc out files in out dirSteve Reinhardt
2019-04-29arch-arm: Faults DebugFlag now printing inst opcode if availableGiacomo Travaglini
2019-04-29arch-arm: Report real instruction encoding when UndefinedGiacomo Travaglini
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
2019-04-28mem: Remove the ISA specialized versions of port proxy's read/write.Gabe Black
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-04-27python: Get rid of the VectorPort constructor.Gabe Black
2019-04-27python: Replace the Master/Slave Ports with Request/Response ports.Gabe Black
2019-04-26arch-arm: updateMiscReg not setting isHyp in aarch64Giacomo Travaglini
2019-04-26arm: Factor some repetition out of the ProcessInfo constructor.Gabe Black
2019-04-25arm: Fix some style issues in stacktrace.cc.Gabe Black
2019-04-25x86: Refactor the ProcessInfo constructor.Gabe Black
2019-04-25x86: Fix some style issues in stacktrace.cc.Gabe Black
2019-04-25sim-se: add a faux-filesystemDavid Hashe
2019-04-25arch-arm: Remove un-needed hyp flag in TLBI operationsGiacomo Travaglini
2019-04-25arch-arm: Correct target EL field in TLBI operationsGiacomo Travaglini
2019-04-25dev-arm: Move GICv3 (Re)Ditributor address in Realview.pyGiacomo Travaglini
2019-04-25dev-arm: Limit number of max PE in GICv3 to 128Giacomo Travaglini
2019-04-25dev-arm: Add GICv4 extension switch in GICv3Giacomo Travaglini
2019-04-25dev-arm: Check for maximum number of supported PE in GICv3Giacomo Travaglini
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-23 00:20:56 +0000