gem5 - gem5

Age	Commit message (Collapse)	Author
2011-03-17	ARM: Fix subtle bug in LDM.	Ali Saidi
	If the instruction faults mid-op the base register shouldn't be written back.
2011-03-17	ARM: Implement the Instruction Set Attribute Registers (ISAR).	Ali Saidi
	The ISAR registers describe which features the processor supports. Transcribe the values listed in section B5.2.5 of the ARM ARM into the registers as read-only values
2011-03-17	ARM: Identify branches as conditional or unconditional and direct or indirect.	Ali Saidi

2011-03-17	ARM: Fix small bug with VLDM/VSTM instructions.	Ali Saidi

2011-03-17	ARM: Detect and skip udelay() functions in linux kernel.	Ali Saidi
	This change speeds up booting, especially in MP cases, by not executing udelay() on the core but instead skipping ahead tha amount of time that is being delayed.
2011-03-17	ARM: Allow conditional quiesce instructions.	Ali Saidi
	This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage.
2011-03-17	ARM: Fix RFE macrop.	Matt Horsnell
	This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes.
2011-03-17	ARM: Rename registers used as temporary state by microops.	Matt Horsnell

2011-03-17	O3: Send instruction back to fetch on squash to seed predecoder correctly.	Ali Saidi

2011-03-17	O3: Cleanup the commitInfo comm struct.	Ali Saidi
	Get rid of unused members and use base types rather than derrived values where possible to limit amount of state.
2011-03-17	ARM: Previous change didn't end up setting instFlags, this does.	Ali Saidi

2011-03-17	Mem: Fix issue with dirty block being lost when entire block transferred to ↵	Ali Saidi
	non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues.
2011-03-17	O3: Fix unaligned stores when cache blocked	Ali Saidi
	Without this change the a store can be issued to the cache multiple times. If this case occurs when the l1 cache is out of mshrs (and thus blocked) the processor will never make forward progress because each cycle it will send a single request using the recently freed mshr and not completing the multipart store. This will continue forever.
2011-03-11	SCons: Stop embedding the mercurial revision into the binary.	Gabe Black
	This causes a lot of rebuilds that could have otherwise possibly been avoided, and, more annoyingly, a lot of unnecessary rerunning of the regressions. The benefits of having the revision in the output haven't materialized, so this change removes it.
2011-03-11	Gems: Eliminate the now unused GEMS_ROOT scons variable.	Gabe Black

2011-03-11	Ruby: Get rid of the dead ruby tester.	Gabe Black
	None of the code in the ruby tester directory is compiled or referred to outside of that directory. This change eliminates it. If it's needed in the future, it can be revived from the history. In the mean time, this removes clutter and the only use of the GEMS_ROOT scons variable.
2011-03-08	Alpha: Fix the datatypes of some values read from the simulated kernel.	Yi Xiang

2011-03-03	SCons: Clean up some inconsistent capitalization in scons options.	Gabe Black

2011-03-02	X86: Use the npc as the pc when doing a nativetrace, not what M5 considers ↵	Gabe Black
	the pc.
2011-03-02	X86: Decode the mysterious and elusive ffreep x87 instruction.	Gabe Black
	The internet says this instruction was created by accident when an Intel CPU failed to decode x87 instructions properly. It's been documented on a few rare occasions and has generally worked to ensure backwards compatability. One source claims that the gcc toolchain is basically the only thing that emits it, and that emulators/binary translators like qemu and bochs implement it. We won't actually implement it here since we're hardly implementing any other x87 instructions either. If we were to implement it, it would behave the same as ffree but then also pop the register stack. http://www.pagetable.com/?p=16
2011-03-01	Spelling: Fix the a spelling error by changing mmaped to mmapped.	Gabe Black
	There may not be a formally correct spelling for the past tense of mmap, but mmapped is the spelling Google doesn't try to autocorrect. This makes sense because it mirrors the past tense of map->mapped and not the past tense of cape->caped. --HG-- rename : src/arch/alpha/mmaped_ipr.hh => src/arch/alpha/mmapped_ipr.hh rename : src/arch/arm/mmaped_ipr.hh => src/arch/arm/mmapped_ipr.hh rename : src/arch/mips/mmaped_ipr.hh => src/arch/mips/mmapped_ipr.hh rename : src/arch/power/mmaped_ipr.hh => src/arch/power/mmapped_ipr.hh rename : src/arch/sparc/mmaped_ipr.hh => src/arch/sparc/mmapped_ipr.hh rename : src/arch/x86/mmaped_ipr.hh => src/arch/x86/mmapped_ipr.hh
2011-03-01	X86: Mark IO reads and writes as non-speculative.	Gabe Black

2011-03-01	X86: Mark prefetches as such in their instruction and request flags.	Gabe Black

2011-03-01	Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer	Nilay Vaish
	At a couple of places in PerfectSwitch.cc and MessageBuffer.cc, DPRINTF() has not been provided with correct number of arguments. The patch fixes these bugs.
2011-03-01	Ruby: Mention that Ruby's bound checking option only applies to Ruby.	Gabe Black

2011-02-27	X86: If PCI config space is disabled, pass through to regular IO addresses.	Gabe Black

2011-02-27	X86: Use regular read requests in the walker instead of read exclusive.	Gabe Black

2011-02-26	getopt: Remove GPL code.	Nathan Binkert
	This code is unused and should never have been committed
2011-02-25	Ruby: Remove store buffer	Nilay Vaish
	This patch removes the store buffer from Ruby. It is not in use currently. Since libruby is being and store buffer makes calls to libruby, it is not possible to maintain it until substantial changes are made.
2011-02-25	Ruby: Remove libruby	Nilay Vaish
	This patch removes libruby_internal.hh, libruby.hh and libruby.cc. It moves the contents to libruby.hh to RubyRequest.hh and RubyRequest.cc files.
2011-02-25	Ruby: Make Address.hh independent of RubySystem	Nilay Vaish
	This patch changes Address.hh so that it is not dependent on RubySystem. This dependence seems unecessary. All those functions that depend on RubySystem have been moved to Address.cc file.
2011-02-25	Ruby: Make DataBlock.hh independent of RubySystem	Nilay Vaish
	This patch changes DataBlock.hh so that it is not dependent on RubySystem. This dependence seems unecessary. All those functions that depende on RubySystem have been moved to DataBlock.cc file.
2011-02-25	O3CPU: Fix iqCount and lsqCount SMT fetch policies.	Timothy M. Jones
	Fixes two of the SMT fetch policies in O3CPU that were returning the count of instructions in the IQ or LSQ rather than the thread ID to fetch from.
2011-02-23	ruby: automate permission setting	Brad Beckmann
	This patch integrates permissions with cache and memory states, and then automates the setting of permissions within the generated code. No longer does one need to manually set the permissions within the setState funciton. This patch will faciliate easier functional access support by always correctly setting permissions for both cache and memory states. --HG-- rename : src/mem/slicc/ast/EnumDeclAST.py => src/mem/slicc/ast/StateDeclAST.py rename : src/mem/slicc/ast/TypeFieldEnumAST.py => src/mem/slicc/ast/TypeFieldStateAST.py
2011-02-23	MOESI_hammer: cache probe address clean up	Brad Beckmann

2011-02-23	ruby: cleaned up access permission enum	Brad Beckmann

2011-02-23	ruby: removed unsupported protocol files	Brad Beckmann

2011-02-23	inorder: InstSeqNum bug	Korey Sewell
	Because int and not InstSeqNum was used in a couple of places, you can overflow the int type and thus get wierd bugs when the sequence number is negative (or some wierd value)
2011-02-23	inorder: dyn inst initialization	Korey Sewell
	remove constructors that werent being used (it just gets confusing) use initialization list for all the variables instead of relying on initVars() function
2011-02-23	inorder: cache packet handling	Korey Sewell
	-use a pointer to CacheReqPacket instead of PacketPtr so correct destructors get called on packet deletion - make sure to delete the packet if the cache blocks the sendTiming request or for some reason we dont use the packet - dont overwrite memory requests since in the worst case an instruction will be replaying a request so no need to keep allocating a new request - we dont use retryPkt so delete it - fetch code was split out already, so just assert that this is a memory reference inst. and that the staticInst is available
2011-02-23	Mem: Print out memory when access > 8 bytes	Ali Saidi

2011-02-23	ARM: Set ITSTATE correctly after FlushPipe	Ali Saidi

2011-02-23	ARM: This panic can be hit during misspeculation so it can't exist.	Ali Saidi

2011-02-23	ARM: Bad interworking warn way to noisy when running real code w/misspeculation.	Ali Saidi

2011-02-23	O3: When a prefetch causes a fault, don't record it in the inst	Ali Saidi

2011-02-23	ARM: NEON instruction templates modified to set the predicate flag to false ↵	Giacomo Gabrielli
	when needed.
2011-02-23	O3: If there is an outstanding table walk don't let the inst queue sleep.	Ali Saidi
	If there is an outstanding table walk and no other activity in the CPU it can go to sleep and never wake up. This change makes the instruction queue always active if the CPU is waiting for a store to translate. If Gabe changes the way this code works then the below should be removed as indicated by the todo.
2011-02-23	ARM: Squash state on FPSCR stride or len write.	Ali Saidi

2011-02-23	ARM: Mark store conditionals as such.	Matt Horsnell

2011-02-23	ARM: Do something for ISB, DSB, DMB	Ali Saidi