gem5 - gem5

Age	Commit message (Expand)	Author
2019-02-08	cpu: fixed how O3 CPU executes an exit system call	Tuan Ta
2019-02-08	arch-arm: Fix Virtual interrupts in AArch64	Giacomo Travaglini
2019-02-08	arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30	Giacomo Travaglini
2019-02-08	arch-arm: Allow ArmPPI usage for PMU	Giacomo Travaglini
2019-02-08	arch-arm: Fix initialization of PMU counters	Ruben Ayrapetyan
2019-02-07	configs, arch-arm: Using AddrRange for Realview mem_regions	Giacomo Travaglini
2019-02-07	arch-riscv: Enable support for riscv 32-bit in SE mode.	Austin Harris
2019-02-06	riscv: remove NonSpeculative flag from fence inst	Tuan Ta
2019-02-06	cpu: fix how a thread starts up in MinorCPU	Tuan Ta
2019-02-06	arch-riscv: Initialize interrupt mask	Tuan Ta
2019-02-06	scons: fix unused auto-generated blob variable in clang	Ciro Santilli
2019-02-06	sim: added missed macro definition on MacOS	Andrea Mondelli
2019-02-05	misc: added missing override specifier	Andrea Mondelli
2019-02-05	cpu: Made the Loop Predictor a SimObject	Javier Bueno
2019-02-05	cpu: Made TAGE a SimObject that can be used by other predictors	Jairo Balart
2019-02-05	riscv: Get rid of ISA specific register types in Interrupts.	Austin Harris
2019-02-01	mem-cache: Updated version of the Signature Path Prefetcher	Javier Bueno
2019-02-01	dev, arm: Removed contextId variable	Anouk Van Laer
2019-02-01	cpu, arch: Replace the CCReg type with RegVal.	Gabe Black
2019-01-31	python: Remove getCode() type workaround	Andreas Sandberg
2019-01-31	sim: Prepare C++ side for Python 3	Andreas Sandberg
2019-01-31	power: Get rid of some ISA specific register types.	Gabe Black
2019-01-31	null: Get rid of some register type definitions.	Gabe Black
2019-01-31	mips: Stop using architecture specific register types.	Gabe Black
2019-01-31	alpha: Stop using architecture specific register types.	Gabe Black
2019-01-31	x86: Stop using/defining some ISA specific register types.	Gabe Black
2019-01-31	riscv: Get rid of some ISA specific register types.	Gabe Black
2019-01-31	arch: cpu: Rename FloatRegBits to FloatReg.	Gabe Black
2019-01-30	arch,cpu: Add vector predicate registers	Giacomo Gabrielli
2019-01-30	arch-arm, configs: Create single instance of DTB autogeneration	Giacomo Travaglini
2019-01-25	arch-arm: Remove floatReg operand type	Giacomo Travaglini
2019-01-25	arch-arm: Use VecElem instead of FloatReg for FP instruction	Giacomo Travaglini
2019-01-25	arch: Fix VecElem Operand generation in ISA parser	Giacomo Travaglini
2019-01-25	cpu, arch, arch-arm: Wire unused VecElem code in the O3 model	Giacomo Travaglini
2019-01-25	cpu: O3 rename using the flatIndex instead of index	Giacomo Travaglini
2019-01-25	arch-arm: Inital vector rename mode depending on A32/A64	Giacomo Travaglini
2019-01-25	cpu: Fix VecElemClass bugs in cpu models	Giacomo Travaglini
2019-01-25	cpu: Add VecElem entries in MinorCPU Scoreboard	Giacomo Travaglini
2019-01-25	arch-arm: Remove unused float operands	Giacomo Travaglini
2019-01-25	arch: Provide traceback when parsing ISA code	Giacomo Travaglini
2019-01-25	python: Always throw TypeError on slave-slave connections	Nicholas Lindsay
2019-01-24	hsail: Remove the MiscReg type.	Gabe Black
2019-01-24	base: arch: Get rid of the now unused FloatRegVal type.	Gabe Black
2019-01-24	dev-arm: fix --generate-dtb for ARM	Ciro Santilli
2019-01-24	cpu-o3: O3 LSQ Generalisation	Rekai Gonzalez-Alberquilla
2019-01-23	arch-arm: Implement LoadAcquire/StoreRelease in AArch32	Giacomo Travaglini
2019-01-23	arch-arm: IsStoreConditional flag set depending on flavor	Giacomo Travaglini
2019-01-23	arch-arm: Remove SWP and SWPB instructions	Giacomo Travaglini
2019-01-23	systemc: Fix TLM related includes.	Gabe Black
2019-01-23	arm: Replace MiscReg with RegVal in utility.(hh\|cc).	Gabe Black