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AgeCommit message (Expand)Author
2019-04-24cpu,mem: missing override specifierAndrea Mondelli
2019-04-24systemc: Use the new TLM socket types in the TLM bridge SimObjects.Gabe Black
2019-04-24systemc: Add Port types for initiator and target sockets.Gabe Black
2019-04-24dev: Use the new Port role mechanism to make an EtherInt Port type.Gabe Black
2019-04-24python: Generalize the Port.splice function.Gabe Black
2019-04-24python: Generalize the dot_writer to handle non Master/Slave roles.Gabe Black
2019-04-24python: Make Port roles a more generic concept.Gabe Black
2019-04-23python: fix tracing after Python 3 refactorCiro Santilli
2019-04-22sim-se: Enhance clone for X86KvmCPUAlexandru Dutu
2019-04-22mem-cache: Fix fix of replacement countDaniel
2019-04-22cpu: Eliminate the ProxyThreadContext class.Gabe Black
2019-04-19mem-cache: Fix increasing replacement countDaniel R. Carvalho
2019-04-19mem-cache: Remove blk_addr from Queue::trySatisfyFunctionalDaniel R. Carvalho
2019-04-19mem-cache: Add match functions to QueueEntryDaniel R. Carvalho
2019-04-19mem: Add packet matching functionsDaniel R. Carvalho
2019-04-19mem-cache: Move Target to QueueEntryDaniel R. Carvalho
2019-04-19mem-cache: Assert Entry inherits from QueueEntry in QueueDaniel R. Carvalho
2019-04-19mem: Make DRAMCtrl::decodeAddr constDaniel R. Carvalho
2019-04-19mem: Allow packet to provide its own addr rangeDaniel R. Carvalho
2019-04-16mem: missing override specifierAndrea Mondelli
2019-04-14mem: Teach SimpleMem to return a MemBackdoor when appropriate.Gabe Black
2019-04-14mem: Maintain a back door into the AbstractMem's backing store.Gabe Black
2019-04-11mem-cache: Fix RRPV for RRIPAnis Peysieux
2019-04-11arch-arm: Enable PMSELR_EL0 read in PMUGiacomo Travaglini
2019-04-10mem: Plumb backdoor requests through the xbar classes.Gabe Black
2019-04-10systemc: Teach the TLM bridges how to use gem5's new backdoor mechanism.Gabe Black
2019-04-10mem: Add sendAtomicBackdoor/recvAtomicBackdoor port methods.Gabe Black
2019-04-10mem-cache: Fix MSHR handling of cache clean requestsNikos Nikoleris
2019-04-10cpu: O3 switchFreeList checking VecElems instead of FloatRegsGiacomo Travaglini
2019-04-08learning_gem5: Fix vector port panic in SimpleCacheJason Lowe-Power
2019-04-06mem: Add a MemBackdoor type to track memory backdoors.Gabe Black
2019-04-05cpu: Correctly account for executed instructions in simple cpusNikos Nikoleris
2019-04-05mem-cache: ambiguous use of abs functionRyan Gambord
2019-04-05mem: Reverse order of write/read mem queue checkJason Lowe-Power
2019-04-04mem-cache: AMPM Prefetcher fails when restoring from a checkpointJavier Bueno
2019-04-03misc: Removed inconsistency in O3* debug msgsAndrea Mondelli
2019-04-03arch-mips: added missing override specifier (o3)Andrea Mondelli
2019-04-03mem-cache: Fix PIF prefetcher compilation error with NULL ISAJavier Bueno
2019-04-03mem-cache: ISB prefetcher was triggering an assertionJavier Bueno
2019-04-03mem-cache: Fix panic in Indirect Memory prefetcherJavier Bueno
2019-04-02dev-arm: Make GICv3 maintenance interrupt an ArmInterruptGiacomo Travaglini
2019-04-02mem-cache: Proactive Instruction Fetch ImplementationIvan Pizarro
2019-04-01dev-arm: Correct cast of template parameterAndrea Mondelli
2019-03-29systemc: Templatize the gem5/TLM bridge SimObjects.Gabe Black
2019-03-29systemc: Delete extra code from src/systemc/tlm_bridge.Gabe Black
2019-03-29systemc: Create unified gem5/TLM bridge SimObjects.Gabe Black
2019-03-29tlm: Initial import of tlm/gem5 bridge code.Gabe Black
2019-03-29systemc: Provide a utility Port TLM socket wrapper class.Gabe Black
2019-03-28cpu: Added a probe to notify the address of retired instructionsJavier Bueno
2019-03-28mem-cache: Remove extra cache header from AMAPDaniel R. Carvalho
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