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AgeCommit message (Expand)Author
2013-06-03base: Make the Python module loader PEP302 compliantAndreas Sandberg
2013-06-03kvm: Allow architectures to override the cycle accounting mechanismAndreas Sandberg
2013-06-03kvm: Add handling of EAGAIN when creating timersAndreas Sandberg
2013-06-03sim: Add debug output when executing pseudo-instructionsAndreas Sandberg
2013-06-03kvm: Add a call to thread->startup() in startup()Andreas Sandberg
2013-06-03dev: Add support for disabling ticking and the divider in MC146818Andreas Sandberg
2013-06-03dev: Clean up MC146818 register (A & B) handlingAndreas Sandberg
2013-05-30mem: More descriptive DRAM config namesAndreas Hansson
2013-05-30mem: Add bytes per activate DRAM controller statAndreas Hansson
2013-05-30mem: Add static latency to the DRAM controllerAndreas Hansson
2013-05-30mem: Spring cleaning of MSHR and MSHRQueueAndreas Hansson
2013-05-30mem: Fix MSHR print formatAndreas Hansson
2013-05-30cpu: Prune the stale TraceCPUAndreas Hansson
2013-05-30cpu: Check that minimum TrafficGen period is less than max periodSascha Bischoff
2013-05-30cpu: Fix bug when reading in TrafficGen state transitionsSascha Bischoff
2013-05-30cpu: Add request elasticity to the traffic generatorAndreas Hansson
2013-05-30cpu: Block traffic generator when requests have to retryAndreas Hansson
2013-05-30cpu: Move traffic generator sending out of generator statesAndreas Hansson
2013-05-30cpu: Fold together the StateGraph and the TrafficGenAndreas Hansson
2013-05-30mem: Make returning snoop responses occupy response layerAndreas Hansson
2013-05-30mem: Make the buses multi layeredAndreas Hansson
2013-05-30mem: Separate the two snoop response cases in the busAndreas Hansson
2013-05-30mem: Tidy up a few variables in the busAndreas Hansson
2013-05-30mem: Add basic stats to the busesUri Wiener
2013-05-30mem: Use unordered set in bus request trackingAndreas Hansson
2013-05-30mem: Check for waiting state in bus drainingAndreas Hansson
2013-05-30mem: Add a LPDDR3-1600 configurationAndreas Hansson
2013-05-30mem: Adapt the LPDDR2 to match a single x32 channelAndreas Hansson
2013-05-30mem: Avoid explicitly zeroing the memory backing storeAndreas Hansson
2013-05-30base: Avoid size limitation on protobuf coded streamsAndreas Hansson
2013-05-30cpu: Make hash struct instead of class to please clangAndreas Hansson
2013-05-21ruby: slicc: fix error msg in TypeFieldMemberAST.pyMalek Musleh
2013-05-21x86: Squash outstanding walks when instructions are squashed.Gedare Bloom
2013-05-21x86: mark instructions for being function call/returnNilay Vaish
2013-05-21x86: add op class for int and fp microops in isa descriptionNilay Vaish
2013-05-21ruby: moesi hammer: cosmetic changesNilay Vaish
2013-05-21ruby: mesi cmp directory: cosmetic changesNilay Vaish
2013-05-21ruby: moesi cmp token: cosmetic changesNilay Vaish
2013-05-21ruby: moesi cmp directory: cosmetic changesNilay Vaish
2013-05-21ruby: add stats to .sm files, remove cache profilerNilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E)
2013-05-14cpu: remove local/globalHistoryBits params from branch predAnthony Gutierrez
2013-05-14kvm: Add support for disabling coalesced MMIOAndreas Sandberg
2013-05-14kvm: Dump state before panic in KVM exit handlersAndreas Sandberg
2013-05-14kvm: Fix the memory interface used by KVMAndreas Sandberg
2013-05-14arm: Add support for the m5fail pseudo-opAndreas Sandberg
2013-05-02kvm: Add a stat counting number of instructions executedAndreas Sandberg
2013-05-02kvm: Add checkpoint debug printAndreas Sandberg
2013-05-02kvm: Make MMIO requests uncacheableAndreas Sandberg
2013-05-02sim: Add support for m5fail in pseudoInst()Andreas Sandberg
2013-04-23x86: corrects vsyscall address for gettimeofdayMichael Levenhagen
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