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2018-01-16sim: Simplify registerThreadContext a little bit.Gabe Black
The code in this function was a little convoluted. This change attempts to simplify it a little bit to make it easier to read. Change-Id: I1ae557b9fede47fa89a9ea550bd0af8ad242449f Reviewed-on: https://gem5-review.googlesource.com/7421 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-15mem: Track TLB entries in the lookup cache as pointers.Gabe Black
Using the architectural page table on x86 and the functional page table on ARM, both with the twolf benchmark in SE mode, there was no performance penalty for doing so, and again possibly a performance improvement. By using a pointer instead of an inline instance, it's possible for the actual type of the TLB entry to be hidden somewhat, taking a step towards abstracting away another aspect of the ISAs. Since the TLB entries are no longer overwritten and now need to be allocated and freed, this change introduces return types from the updateCache and eraseCacheEntry functions. These functions will return the pointer to any entry which has been displaced from the cache which the caller can either free or ignore, depending on whether the entry has a purpose outside of the cache. Because the functional page table stores its entries over a longer time period, it will generally not delete the pointer returned from those functions. The "architechtural" page table, ie the one which is backed by memory, doesn't have any other use for the TlbEntrys and will delete them. That leads to more news and deletes than there used to be. To address that, and also to speed up the architectural page table in general, it would be a good idea to augment the functional page table with an image of the table in memory, instead of replacing it with one. The functional page table would provide quick lookups and also avoid having to translate page table entries to TLB entries, making performance essentially equivalent to the functional case. The backing page tables, which are primarily for consumption by the physical hardware when in KVM, can be updated when mappings change but otherwise left alone. If we end up doing that, we could just let the ISA specific process classes enable whatever additional TLB machinery they need, likely a backing copy in memory, without any knowledge or involvement from the ISA agnostic class. We would be able to get rid of the useArchPT setting and the bits of code in the configs which set it. Change-Id: I2e21945cd852bb1b3d0740fe6a4c5acbfd9548c5 Reviewed-on: https://gem5-review.googlesource.com/6983 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-01-15arch: Fix a fatal_if in most of the arch's process classes.Gabe Black
When switching an assert to a fatal while addressing recent review feedback, I forgot to reverse the polarity of the condition, making the fatal fire in exactly the opposite of the conditions it was meant to. Change-Id: Icf49864ef449052bbb0d427dca786006166575c4 Reviewed-on: https://gem5-review.googlesource.com/7381 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-12sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().Xiaoyu Ma
Before this CL, the addTwoLevelCacheHierarchy() function uses the default L2XBar class as the interconnect between CPU L1 caches and L2. This CL allows passing a user-defined bus to overwrite the default L2XBar by adding an optional argument to the function. Change-Id: I917657272fd4924ee0bed882a226851afba26847 Reviewed-on: https://gem5-review.googlesource.com/7364 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-11arch-riscv: Don't crash when printing unknown CSRsAlec Roelke
This patch fixes a potential crash if an unnamed CSR is accessed and debug flags are enabled that print disassembly. Unknown CSRs will be identified as "??" followed by the address that was used. Change-Id: If5ac57f1422bd59c72a1a06206fa9d9dc05d21ef Reviewed-on: https://gem5-review.googlesource.com/7321 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-01-11mem-ruby: Fix wakeup timeouts for the MOESI_CMP_token protocolNikos Nikoleris
This changeset fixes a bug that was affecting the MOESI_CMP_token protocol where setting the next timeout required an absolute tick in the future. Change-Id: Ibfdb59354e13c7e552cb3389e71bda010f333249 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7163 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-11mem-ruby: Remove function that maps responses to a DMA engineNikos Nikoleris
The function map_Address_to_DMA was used to route responses to the first (and assumed to be the only) DMA engine in the system. This function is now unused as protocols handle responses and route them to the right DMA engine. Change-Id: I2fba913cf2f12321d1a1e38e7ee85bdf26b8a47a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7162 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-11mem-ruby: Add support for multiple DMA engines in MESI_Two_LevelNikos Nikoleris
Previously the MESI_Two_Level protocol supported systems with a single DMA engine and responses from the directory to DMA requests were routed back to the only DMA engine. This changeset adds support for multiple DMA engines in the system by routing the response to the DMA engine that originally sent the request. Change-Id: I10ceda682ea29746636862ec8ef2a9c4220ca045 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7161 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-11cpu: Make the CPU's TLB parameter a BaseTLB.Gabe Black
This is instead of the architecture specific version. Change-Id: I906ec16eee1f65f0e9b9c24b401430f9ea01637b Reviewed-on: https://gem5-review.googlesource.com/7349 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-11arm, power: Make the python TLB simobjects inherit from BaseTLB.Gabe Black
These were still inheriting from SimObject instead of BaseTLB, making them incompatible with parameters which expect a BaseTLB. Change-Id: I05115cc5515f745fdeb85e4dea8eded613647e40 Reviewed-on: https://gem5-review.googlesource.com/7348 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-11arch,mem: Remove the default value for page size.Gabe Black
This breaks one more architecture dependence outside of the ISAs. Change-Id: I071f9ed73aef78e1cd1752247c183e30854b2d28 Reviewed-on: https://gem5-review.googlesource.com/6982 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2018-01-11arch,mem: Move page table construction into the arch classes.Gabe Black
This gets rid of an awkward NoArchPageTable class, and also gives the arch a place to inject ISA specific parameters (specifically page size) without having to have TheISA:: in the generic version of these types. Change-Id: I1412f303460d5c43dafdb9b3cd07af81c908a441 Reviewed-on: https://gem5-review.googlesource.com/6981 Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-10style: change C/C++ source permissions to noexecBKP
Several files in the repository were tracked with execute permissions even though the files are just normal C/C++ files (and the one .isa). Change-Id: I976b096acab4a1fc74c5699ef1f9b222c1e635c2 Reviewed-on: https://gem5-review.googlesource.com/7241 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-10arch-riscv: Make use of ImmOp's polymorphismAlec Roelke
This patch makes use of ImmOp's polymorphism to remove unnecessary casting from the implementations of arithmetic instructions with immediate operands and to remove the CUIOp format by combining it with the CIOp format (compressed arithmetic instructions with immediate operands). Interestingly, RISC-V specifies that instructions with unsigned immediate operands still need to sign-extend the immediates from 12 (or 20) bits to 64 bits, so that is left alone. Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16 Reviewed-on: https://gem5-review.googlesource.com/6401 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-01-10alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.Gabe Black
This constant is, first, a #define, and second only used in one place. In that one place, it appears that the code it guards is no longer necessary in general. It was originally written to avoid refetching a block of data that you're still in, even if you've moved slightly farther in it because you're skipping the next instruction due to an annulled branch delay slot. In reality however, in SPARC, the one ISA I'm aware of which has this sort of branching behavior, the PC state object will correctly determine that no branch is happening in these cases. Code lower down in the loop will then recompute where fetching should continue based on the next PC, automatically skipping the annulled branch slot without misinterpretting the gap as a branch. This change therefore also removes this block of code. Change-Id: I820ebc9df10aeb4fcb69c12f6a784e9ec616743c Reviewed-on: https://gem5-review.googlesource.com/6821 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-10arch-riscv,sim: Support clone syscall in RISC-VTuan Ta
(1) This patch sets a correct order of clone syscall's arguments for RISC-V. Linux kernel 4.15 uses CLONE_BACKWARDS flag by default for RISC-V. The flag in the Linux kernel defines the list of clone syscall's arguments in the following order: clone_flags (flags) newsp (newStack) parent_tidptr (ptidPtr) tls (tlsPtr) child_tidptr (ctidPtr) Code reference: https://github.com/riscv/riscv-linux/blob/master/kernel/fork.c https://github.com/riscv/riscv-linux/blob/master/arch/riscv/Kconfig (2) This patch copies a parent thread's register values to its child thread in clone syscall. Change-Id: I2eb1c8e80990861080ce7153503ed784fb2c7bdf Reviewed-on: https://gem5-review.googlesource.com/6904 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
2018-01-09mem-cache: Prune unnecessary writebacks in exclusive cachesNikos Nikoleris
Exclusive caches use the tempBlock to fill for responses from a downstream cache. The reason for this is that they only pass the block to the cache above without keeping a copy. When all requests are serviced the block is immediately invalidated unless it is dirty, in which case it has to be written back to the memory below. To avoid unnecessary writebacks, this changeset forces mostly exclusive caches to issuse requests that can only fetch clean data when possible. Reported-by: Quereshi Muhammad Avais <avais@kaist.ac.kr> Change-Id: I01b377563f5aa3e12d22f425a04db7c023071849 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-01-09cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults.Gabe Black
When a fault happens in fetch in O3, a dummy inst is created to carry the fault through the pipeline to commit, but conceptually there isn't actually any instruction since we failed to fetch one. This change marks the dummy instruction as NotAnInst, and when any such instruction gets to commit, the fault object associated with it is invoked and passed a null static inst pointer instead of a pointer to the dummy inst. Change-Id: I18d993083406deb625402e06af4ba0d4772ca5a3 Reviewed-on: https://gem5-review.googlesource.com/7124 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-09cpu: Add a NotAnInst flag to the BaseDynInst class.Gabe Black
This flag means that the instruction isn't an actual instruction, it's just a placeholder to carry a fault down a pipeline, for instance. Change-Id: I1cc12b068662dbd3d3b089c9941a07b6e88b57e3 Reviewed-on: https://gem5-review.googlesource.com/7123 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-09cpu, power: Get rid of the remnants of the EA computation insts.Gabe Black
Get rid of some remnants of a system which was intended to separate address computation into its own instruction object. Change-Id: I23f9ffd70fcb89a8ea5bbb934507fb00da9a0b7f Reviewed-on: https://gem5-review.googlesource.com/7122 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-09arm: Make translateFunctional override the base implementation.Gabe Black
Now that translateFunctional is a virtual function, having an extra parameter with a default value makes the compiler fall through to the base implementation instead of overriding it. This change removes the default value for the extra parameter, and adds a small wrapper with the correct signature which overrides the base implementation and calls the full version with the previously default value for the extra parameter. To callers this will look like the same thing, but the the right function will get called. This was what was already being done for transateAtomic and translateTiming. Change-Id: I0b71adf34fd6f326005edbb8eaac93275b437c55 Reviewed-on: https://gem5-review.googlesource.com/7121 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-05arch-riscv: Ignore sched_yield syscall in SE modeTuan Ta
Change-Id: I14f22c06eb8fdbe063980b4cd0a49387b9113a97 Reviewed-on: https://gem5-review.googlesource.com/6961 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
2018-01-05sim: Fix a bug in prlimit syscall in SE modeTuan Ta
The old_limit pointer is supposed to be the 4th argument (index 3) of the prlimit syscall. This patch sets old_limit pointer to the correct argument. Change-Id: I97808f7234cd2622cb3eb2f1e0beb7fc8cf492c1 Reviewed-on: https://gem5-review.googlesource.com/6903 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-01-05arch-riscv: Ignore set_robust_list and get_robust_list syscallsTuan Ta
Change-Id: I5a4744e5aed07337144af9f07978b83405b6695b Reviewed-on: https://gem5-review.googlesource.com/6902 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-01-05arch-riscv: Add an implementation of set_tid_address syscall in RISCVTuan Ta
Change-Id: Ida29ea6f6a9c3efe00aaebbfcb6b537fc62f6d06 Reviewed-on: https://gem5-review.googlesource.com/6901 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-01-05arch-riscv: Correct syscall argument reg countAlec Roelke
As per the discussion in patch #6904 and the Linux 4.15 kernel code for RISC-V, RISC-V has 7 system call argument registers, x10 through x16 (a0 through a6), with x17 (a7) being used for the system call number. Change-Id: I0080eca78ffa844b322bb2cff2a51ab2815f3809 Reviewed-on: https://gem5-review.googlesource.com/7081 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-01-04arch-riscv: Remove "magic" syscall number constantAlec Roelke
getSyscallArg() in RISC-V has an explicit check to make sure that the register index is within the bounds of the system call register indices vector. This patch fixes it so that it uses SyscallArgumentRegs.size() rather than a "magic" constant that has to be updated every time SyscallArgumentRegs is changed. Change-Id: I2935d811177dc8028cb3df64b250ba997bc970d8 Reviewed-on: https://gem5-review.googlesource.com/7061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-12-23alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.Gabe Black
It's no longer used. Change-Id: I4a71bcb214f1bb186b92ef50841eca635e6701c5 Reviewed-on: https://gem5-review.googlesource.com/6826 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-23riscv,x86: Stop using the arch Nop machine instruction unnecessarily.Gabe Black
That particular ExtMachInst is a convenient placeholder, but a value of 0 in RISCV or a static uninitialized ExtMachInst (which will therefore be all zeroes) on x86 works just as well, and removes the need for an ISA specific constant. Also, the idea of a universal Nop doesn't always make sense since it could be that what, exactly, doesn't do anything depends on context which would be lost on a constant value of an ExtMachInst. For instance, the value of an ExtMachInst that makes sense might depend on what mode the CPU was in, etc. Change-Id: I1f1a43a5c607a667e11b79bcf6e059e4f7141b3f Reviewed-on: https://gem5-review.googlesource.com/6825 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
CPUs have historically instantiated the architecture specific version of the TLBs to avoid a virtual function call, making them a little bit more dependent on what the current ISA is. Some simple performance measurement, the x86 twolf regression on the atomic CPU, shows that there isn't actually any performance benefit, and if anything the simulator goes slightly faster (although still within margin of error) when the TLB functions are virtual. This change switches everything outside of the architectures themselves to use the generic BaseTLB type, and then inside the ISA for them to cast that to their architecture specific type to call into architecture specific interfaces. The ARM TLB needed the most adjustment since it was using non-standard translation function signatures. Specifically, they all took an extra "type" parameter which defaulted to normal, and translateTiming returned a Fault. translateTiming actually doesn't need to return a Fault because everywhere that consumed it just stored it into a structure which it then deleted(?), and the fault is stored in the Translation object when the translation is done. A little more work is needed to fully obviate the arch/tlb.hh header, so the TheISA::TLB type is still visible outside of the ISAs. Specifically, the TlbEntry type is used in the generic PageTable which lives in src/mem. Change-Id: I51b68ee74411f9af778317eff222f9349d2ed575 Reviewed-on: https://gem5-review.googlesource.com/6921 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-22cpu: Use the generic nop static inst instead of decoding the arch version.Gabe Black
This removes a dependence on the ISA. Change-Id: I01013bc70558f0831327213912bcac11258066a6 Reviewed-on: https://gem5-review.googlesource.com/6824 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-22cpu: Add a pointer to a generic Nop StaticInst.Gabe Black
This can be used whenever generic code needs a filler instruction that doesn't do anything. Change-Id: Ib245d3e880a951e229eb315a09ecc7c47e6ae00f Reviewed-on: https://gem5-review.googlesource.com/6823 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-21arch-arm: Fixed WFE/WFI trapping behaviourGiacomo Travaglini
This patch fixes the WFx trapping behaviour by introducing the arm arm v8 pseudocode functions: checkForWFxTrap32 and checkForWFxTrap64 Change-Id: I3db0d78b5c4ad46860e6d199c2f2fc7b41842840 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6622 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-21arch-arm: Hyp routed undef fault need to change its syndromeGiacomo Travaglini
If undefined instruction has to be routed to EL2, the HSR register must change the HSR.EC and HSR.ISS accordingly, which means not using the EL1 exception syndrome, but the unknown reason one (EC=0, ISS=0) Change-Id: I1540c713ab545bf307c1dad3ae305de4178443f4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6621 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-21arch-arm: Fix StaticInst encoding() methodGiacomo Travaglini
The previously introduced method was missing the machInst value to be masked. Change-Id: Ic722f7cc2abc680da1a1f19c08299338b5c859a6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chuan Zhu <chuan.zhu@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6881 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-20cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh.Gabe Black
Change-Id: I868021a01eb3e7902a4d64283bdfaa93c6d9f964 Reviewed-on: https://gem5-review.googlesource.com/6822 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-19arch-arm: Instruction size methods in StaticInst classGiacomo Travaglini
This patch is introducing some methods in StaticInst so that is possible to get the instruction size in byte of the instruction (can be 2 bytes in Thumb) and the correct opcode (The machInst field contains some appended metadata) Change-Id: I3bed4d9fd7c77feaeded40ded192afe445d306ea Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6781 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-19arch-arm: Change casting type from reinterpret to staticGiacomo Travaglini
Cosmetic fix: prefer static_cast rather than reinterpret_cast in hierarchy. Change-Id: Ic0e5a4df9b18072a6df5ee316f674241074c349a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6761 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-19cpu-tester: Added ExitGen to TrafficGenRiken Gohil
Added the ExitGen to the TrafficGenerator which allows an EXIT state to be added to the TrafficGen configuration file. Entering this state will cause the simulation to exit immediately. Please note that if multiple TrafficGen instances have an EXIT state, the first of these to be encountered will cause the simulation to terminate. Change-Id: Ieea51f05ffb780771f007787a2b119f79143d0c1 Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5723 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-19cpu-tester: Refactoring traffic generators into separate files.Riken Gohil
Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013 Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5722 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-15mem-ruby: Support atomic_noncaching acceses in rubySwapnil Haria
Ruby has no support for atomic_noncaching accesses, which prevents using it with kvm-cpu. This patch fixes this by directly forwarding atomic requests from the ruby port/sequencer to the corresponding directory based on the destination address of the packet. Change-Id: I0b4928bfda44fd9e5e48583c51d1ea422800da2d Reviewed-on: https://gem5-review.googlesource.com/5601 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2017-12-14arch-riscv: Define AT_RANDOM properlyAlec Roelke
According to the getauxval(3) man page, the AT_RANDOM aux value should be a pointer to 16 random bytes. In the initial implementation of RISC-V, this was based on spike's program stack setup, which copied the program header table there instead. This patch changes the implementation to use the proper 16 random bytes, making it compatible with some RISC-V programs that use custom linker scripts. Change-Id: Idaae7f19bf3ed3fd06d293e5e9c0b6f778270eb2 Reviewed-on: https://gem5-review.googlesource.com/6681 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-12-14arch-riscv: Increase maximum stack sizeAlec Roelke
This patch increases the maximum stack size of RISC-V, which should help to reduce problems with programs that allocate large amounts of data on the stack or do many small allocations. Change-Id: I1d760050229b12f01a4a8f24c047b587299fef6d Reviewed-on: https://gem5-review.googlesource.com/6661 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-12-14misc: Updates for gcc7.2 for x86Jason Lowe-Power
GCC 7.2 is much stricter than previous GCC versions. The following changes are needed: * There is now a warning if there is an implicit fallthrough between two case statments. C++17 adds the [[fallthrough]]; declaration. However, to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH. M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and if that doesn't exist, it defaults to nothing (no older compilers generate warnings). * The above resulted in a couple of bugs that were found. This is noted in the review request on gerrit. * throw() for dynamic exception specification is deprecated * There were a couple of new uninitialized variable warnings * Can no longer perform bitwise operations on a bool. * Must now include <functional> for std::function * Compiler bug for void* lambda. Changed to auto as work around. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878 Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5802 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-12-14x86: Use operand size 4 when it would be 2 for cmpxchg8b.Gabe Black
This means the instruction is treated as cmpxchg8b when the effective operand size is 16 bits. Change-Id: I4d9bb295f96097e1746a9bbccb2c579d14738fab Reviewed-on: https://gem5-review.googlesource.com/6603 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-13scons, tests: Fix occasional linking errorAndreas Sandberg
There are some cases where scons incorrectly adds the same object multiple times to the linker command line. This seems to be caused by the test's source list being updated in place when determining test framework dependencies. Fix this by explicitly copying the source list and manipulate the copy. Without this change, the following command fails: scons ./build/ARM/unittests.opt/base/pixeltest.xml Whereas this command succeeds: scons ./build/ARM/base/pixeltest.opt Change-Id: I642efdf9d62a5478e49ba51efe1a3a5ba453e21f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6641 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2017-12-13scons, tests: Add support for GTest XML generationAndreas Sandberg
The GTest framework supports result generation in XML (JUnit). Enable this by creating unit test specific targets in the build/${BUILD_OPTS}/unittests.${VARIANT} directory. Targets in the directory use the following naming convention: ${SRC_PATH}/${TEST_NAME}.xml For example, the opt version of the bitunion test built for ARM would have this path: build/ARM/unittests.opt/base/bituniontest.xml Change-Id: I174dff16817734db05b08ce1d5bcf52e8697bbac Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6624 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-12-13scons: Make sure GTests have the right environment variablesAndreas Sandberg
SCons currently scrubs the environment variables used by GTests too aggressively. This breaks systems where libraries are installed in non-standard locations that need to be specified in LD_LIBRARY_PATH. Run said tests in the gtest_env SCons environment which white-lists the important environment variables. Change-Id: I5fc8fb5e51f09644dc976ee97b21c78ab349bf7d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6623 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-12-13arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.Gabe Black
Replace them with std::array<>s. Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34 Reviewed-on: https://gem5-review.googlesource.com/6602 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-13cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.Gabe Black
Neither of these were used, particularly memAccInst. Change-Id: I4ac9e44cf624e5de42519d586d7b699f08a2cdfc Reviewed-on: https://gem5-review.googlesource.com/6601 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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