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2019-08-29stats: Add support for hierarchical statsAndreas Sandberg
This change makes the stat system aware of the hierarchical nature of stats. The aim is to achieve the following goals: * Make the SimObject hierarchy explicit in the stat system (i.e., get rid of name() + ".foo"). This makes stat naming less fragile and makes it possible to implement hierarchical formats like XML/HDF5/JSON in a clean way. * Make it more convenient to split stats into a separate struct/class that can be bound to a SimObject. This makes the namespace cleaner and makes stat accesses a bit more obvious. * Make it possible to build groups of stats in C++ that can be used in subcomponents in a SimObject (similar to what we do for checkpoint sections). This makes it easier to structure large components. * Enable partial stat dumps. Some of our internal users have been asking for this since a full stat dump can be large. * Enable better stat access from Python. This changeset implements solves the first three points by introducing a class (Stats::Group) that owns statistics belonging to the same object. SimObjects inherit from Stats::Group since they typically have statistics. New-style statistics need to be associated with a parent group at instantiation time. Instantiation typically sets the name and the description, other parameters need to be set by overriding Group::regStats() just like with legacy stats. Simple objects with scalar stats can typically avoid implementing regStats() altogether since the stat name and description are both specified in the constructor. For convenience reasons, statistics groups can be merged into other groups. This means that a SimObject can create a stat struct that inherits from Stats::Group and merge it into the parent group (SimObject). This can make the code cleaner since statistics tracking gets grouped into a single object. Stat visitors have a new API to expose the group structure. The Output::beginGroup(name) method is called at the beginning of a group and the Output::endGroup() method is called when all stats, and sub-groups, have been visited. Flat formats (e.g., the text format) typically need to maintain a stack to track the full path to a stat. Legacy, flat, statistics are still supported after applying this change. These stats don't belong to any group and stat visitors will not see a Output::beginGroup(name) call before their corresponding Output::visit() methods are called. Change-Id: I9025d61dfadeabcc8ecf30813ab2060def455648 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19368 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2019-08-28mem-ruby: Define BloomFilter namespaceDaniel R. Carvalho
Define a BloomFilter namespace and put all BloomFilter related code in it. As a side effect the BloomFilter classes have been renamed to remove the "BloomFilter" suffix. Change-Id: I3ee8cc225bf3b820e561c3e25a6bf38e0012e3a8 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18874 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-28mem-ruby: Make H3 inherit from MultiBitSelBloomFilterDaniel R. Carvalho
Make MultiBitSelBloomFilter a generic BloomFilter that maps multiple entries to an address, and therefore uses multiple hash functions. This allows the common functionality of both filters to be merged into one, since they only differ in the hash functions being used. Change-Id: I0984067b710a208715f5f2727b8c4312feb6529b Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18873 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-28mem-ruby: Finish implementing BloomFilter mergeDaniel R. Carvalho
Not all Bloom Filters had their union functionality implemented. This change adds them. Change-Id: I86af18d3c5eabd0da8280b57a88789b3af803c04 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18872 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-08-28mem-ruby: Remove NonCountingBloomFilterDaniel R. Carvalho
Make BlockBloomFilter accept having a single bitfield, in which case it behaves exactly as the NonCountingBloomFilter, and thus the latter can be removed. Change-Id: I56d96a89290c933293ce434bbe0e8bcd4bbcaa42 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18871 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-28mem-ruby: Make MultiGrainBloomFilter genericDaniel R. Carvalho
Allow combining any number of Bloom Filters in the MultiGrain. Change-Id: I73ae33063e1feed731af6f625d2f64245f21df18 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18869 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-28mem-ruby: Parameterize xor bits in BlockBloomFilterDaniel R. Carvalho
Parameterize bitfield ranges in BlockBloomFilter such that the hash is applied between masked bitfields of an address. Change-Id: I008bd873458e9815e98530e308491adb65bb34cb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18870 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-08-28cpu: Make get(Data|Inst)Port return a Port and not a MasterPort.Gabe Black
No caller uses any of the MasterPort specific properties of these function's return values, so we can instead return a reference to the base Port class. This makes it possible for the data and inst ports to be of any port type, not just gem5 style MasterPorts. This makes life simpler for, for example, systemc based CPUs which might have TLM ports. It also makes it possible for any two CPUs which have compatible ports to be switched between, as long as the ports they use support being unbound. Unfortunately that does not include TLM or systemc ports which are bound permanently. Change-Id: I98fce5a16d2ef1af051238e929dd96d57a4ac838 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20240 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-08-28cpu, mem: Add new getSendFunctional method to the base CPU.Gabe Black
This returns a sendFunctional delegate references which can be used to send functional accesses directly, or more likely when constructing a PortProxy subclass. In those cases only the functional capabilities of those ports are needed so there's no reason to require a full port which supports all three protocols. Also, this removes the last remaining use of get(Data|Inst)Port which relies on those returning a port which supports the gem5 protocols, except the default implementations of this new function. If a CPU doesn't have traditional gem5 style ports, it can override this function to do whatever other behavior is necessary and return its real ports through get(Data|Inst)Port. Change-Id: Ide4da81e3bc679662cd85902ba6bd537cce54a53 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20237 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-08-28mem: Make PortProxy use a delegate for a sendFunctional function.Gabe Black
The only part of the MaserPort the PortProxy uses is the sendFunctional function which is part of the functional protocol. Rather than require a MasterPort which comes along with a lot of other mechanisms, this change slightly adjusts the PortProxy to only require that function through the use of a delegate. That allows lots of flexibility in how the actual packet gets sent and what sends it. In cases where code constructs a PortProxy and passes its constructor an unbound MasterPort, the PortProxy will create a delegate to the sendFunctional method on its own. This should also make it easier for objects which don't have traditional gem5 style ports, for instance systemc models, to implement just the little bit of the protocol they need, rather than having to stub out a whole port class, most of which will be ignored. Change-Id: I234b42ce050f12313b551a61736186ddf2c9e2c7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20229 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-28cpu: Move the instruction port into o3's fetch stage.Gabe Black
That's where it's used, and that avoids having to pass it around using the top level getInstPort accessor. Change-Id: I489a3f3239b3116292f3dcd78a3945fb468c6311 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20239 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-08-28cpu: Move O3's data port into the LSQ.Gabe Black
That's where it's used, and putting it there avoids having to pass around the port using the top level getDataPort function. Change-Id: I0dea25d0c5f4bb3f58a6574a8f2b2d242784caf2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20238 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-08-28mem: Eliminate the Base(Slave|Master)Port classes.Gabe Black
The Port class has assumed all the duties of the less generic Base*Port classes, making them unnecessary. Since they don't add anything but make the code more complex, this change eliminates them. Change-Id: Ibb9c56def04465f353362595c1f1c5ac5083e5e9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20236 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-08-27cpu, dev, mem: Use the new Port methods.Gabe Black
Use getPeer, takeOverFrom, and << to simplify the use of ports in some areas. Change-Id: Idfbda27411b5d6b742f5e4927894302ea6d6a53d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20235 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-08-27sim: Add a << overload for the Port class which prints its name.Gabe Black
This makes it easier/less verbose to print the name of a port, it's most important and identifying feature, in a DPRINTF or other stream based output. Change-Id: I050d102844612577f9a83d550e619736507a6781 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20234 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-08-27sim: Add a takeOverFrom method to the base Port class.Gabe Black
This makes it easier, safer, and less verbose to swap out ports when a CPU takes over for another CPU, for instance. Change-Id: Ice08e4dcb4b04dc66b1841331092a78b4f6f5a96 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20233 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-08-27mem, sim, systemc: Reorganize Port and co.s bind, unbind slightly.Gabe Black
The base Port class can keep track of its peer, and also whether it's connected. This is partially delegated away from the port subclasses which still keep track of a cast version of their peer pointer for their own conveneince, so that it can be used by generic code. Even with the Port mechanism's new flexibility, each port still has exactly one peer and is either connected or not based on whether there is a peer currently. Change-Id: Id3228617dd1604d196814254a1aadeac5ade7cde Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20232 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-08-26dev-arm: Fix GICv3 ITS indexing errorGiacomo Travaglini
Table walks were not considering the entry size when evaluating the address. Change-Id: Ica6bf6d88632985ee8ed120448b32e0f7e918a8a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20329 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-26dev-arm: Fix GITS_BASER initialization/accessGiacomo Travaglini
The patch is fixing/improving GITS_BASER registers initialization. * Not using reserved table types anymore (GITS_BASER.TYPE) * Using write mask for handling WI bits Change-Id: Ibe24667fdf22b42b86496167c19fc00bbb0ba191 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20328 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-23arch-riscv: fix GDB register cacheAlec Roelke
Fixes the definition of the RISC-V GDB register cache. The latest version, of RISC-V gdb, commit c3eb4078520dad8234ffd7fbf893ac0da23ad3c8, appears to only accept the 32 integer registers + the PC in the 'g' packet. This functions with the Linux toolchain (riscv64-unknown-linux-gnu-*), but works best with the Newlib toolchain (riscv64-unknown-elf-*). Change-Id: Ie35ea89a45870fb634e6c68236261bde27c86e41 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20028 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-23mem: Put gem5 protocols in their own directory.Gabe Black
This reduces clutter in the src/mem directory, and makes it clear that those protocols are for the classic gem5 memory system, not ruby, TLM, etc. Change-Id: I6cf6b21134d82f4f01991e4fe92dbea8c7e82081 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20231 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-08-23mem: Move ruby protocols into a directory called ruby_protocol.Gabe Black
Now that the gem5 protocols are split out, it would be nice to put them in their own protocol directory. It's also confusing to have files called *_protocol which are not in the protocol directory. Change-Id: I7475ee111630050a2421816dfd290921baab9f71 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20230 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-23mem: Split the various protocols out of the gem5 master/slave ports.Gabe Black
This makes the protocols easier to see in their entirity, and makes it easier to add a new type of port which only supports the functional protocol. Change-Id: If5d639bef45062f0a23af2ac46f50933e6a8f144 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20228 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-08-22mem-ruby: fix build with PROTOCOL=MOESI_hammerCiro Santilli
Was failing with: Error: Unrecognized variable: l1i_victim_addr since: I2c43f22aba5af3a57e54b1c435e5d3fbba86d1d5 Change-Id: I7df666acb724ee541804dd7557753a9ba4005516 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20261 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-22dev-arm: Start using GITS_CTLR.quiescent bitGiacomo Travaglini
The GITS_CTLR.quiescent bit is used by priviledged sw to check when the ITS has finished draining its state (all pending translations/table walks have ended) once it has been disabled (by setting the GITS_CTLR.enable bit to 0). This patch is modelling this behaviour by * Changing the reset state to enable=0, quiescent=1 * Making the GITS_CTLR.quiescent bit RO * Updating the bit once a new translation/command is being processed (quiescent=0) and when there are no pending translation/commands (quiescent=1) Change-Id: I7cfe94b25d603400364b1cdfc2d2397acf5dfad8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20257 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-22dev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR/BASER)Giacomo Travaglini
For those registers (GITS_CWRITER, GITS_READR and GITS_CBASER) Bits [63:32] and bits [31:0] are accessible separately. Change-Id: Ibf60b5e4fd20efb21a63570e6012862e37946877 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20256 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-22dev-arm,system-arm: missing GICv3 ranges propertyAdrian Herrera
This patch adds the device tree "ranges" property to GICv3 for the VExpress_GEM5_V2 platform. It is also included in the GICv3 DTB auto generation. This allows the GICv3 ITS to be specified in the device tree. Change-Id: I00e1bb0fd45521e34820c0a23ddf047afec7aa4c Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20255 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-21arch-riscv: Update register fileYifei Liu
This patch adds mcounteren, scounteren according to Risc-V Privileged Architectures V1.10. Change-Id: I6e138a50710bc0a1e9d9c38a11fc7fcc09ed500e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20128 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-21arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0Ciro Santilli
In src/cpu/reg_class.hh, numPinnedWrites was unset because the constructors were not well factored out. Change-Id: Ib2fc8d34a1adf5c48826d257a31dd24dfa64a08a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20048 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-21base: assert that stats bucket size is greater than 0Ciro Santilli
Change-Id: I9a2264e9ee74acea1f09f01ea8f5004567ba1ea8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20049 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-21arch-arm: Fix implicit fallthrough build errorsChun-Chen TK Hsu
1942b21713 introduced implicit-fallthrough errors when compiled with GCC 8. This change adds M5_UNREACHABLE in the default case. Change-Id: I220f2b3fe39b5c3a65c0dd390915bffeafb28962 Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20268 Reviewed-by: Jordi Vaquero <jordi.vaquero@metempsy.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20dev-arm: Add redistributor-stride property to GICv3Giacomo Travaglini
This is needed since by default the model is assuming a GICv4 memory layout. Change-Id: Ic64e6a488cc1a43a56ce28f6d11b8868df102aa0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20248 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currELGiacomo Travaglini
Change-Id: I739a9be03ea5caa63540c62fd110eee86a058c4c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20252 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20arch-arm: Replace direct use cpsr.el with currEL helperGiacomo Travaglini
The patch is replacing it in places where the current EL could be using AArch32, hence leading to an incorrect ExceptionLevel. Change-Id: I99b75af2668f2c38fd88bec62e985ab7dbea80dc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20251 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20arch-arm: Overload currEL helper with CPSR argumentGiacomo Travaglini
Change-Id: I1edabc61637ecb9d30bca34b5dbcf1de12b35fe0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20250 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20arch-arm: Rewrite the currEL helper method to use opModeToELGiacomo Travaglini
Direct use of cpsr.el should be discouraged: it should be used when in AArch64 only; when in AArch32 it won't return the matching EL. Eg: when in Supervisor Mode (EL1), CPSR.M<3,0> (mode) is 0b0011, and cpsr.el will return 0 (EL0) Change-Id: I5504bd1f59980f79b2607cce435ea09245de12e5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20249 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20dev-arm: Add GITS_PIDR2 register to the ITS memory mapGiacomo Travaglini
The GITS Peripheral Identification Register #2 bits assignments are the same as those for GICD_PIDR2. Change-Id: I235008a383e08dd557d899cb3aa18202ef943f8b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20254 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20dev-arm: Add Gicv3Distributor members for GICv3 GICD_PIDRxGiacomo Travaglini
There is no need of calculating the value every time the registers are read. Change-Id: I58b87abb585fb9928959992927f00d9c000a4c35 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20253 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-19mem-ruby, arch-hsail: Removed hit latency from VIPERCoalescerPablo Prieto
Removed the dcache hit latency from VIPERCoalescer so HSAIL_X86 compiles after commit 496d5ed3e1f7dad42b0c2ebe0050d84621be8f99 Change-Id: I050a58d90f0f6356824c3c3bcb3f0b3c76d145e0 Signed-off-by: Pablo Prieto <pablo.prieto@unican.es> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19148 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-16x86: Stop CPUID from claiming we support xsave.Gabe Black
xsave is a fairly complex feature which we don't support in gem5, but we do report that we support it through CPUID. It looks like I confused it with FXSAVE which is an instruction related to SSE. This change turns that bit back off again. Change-Id: I00fc79168c5f7095b5241e870a4c8782e4385425 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20169 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-15x86: Make unsuccessful CPUID instructions zero the result.Gabe Black
The previous implementation left the registers unmodified which is technically correct since there is no defined behavior in that case or a fault to raise. That would make what happened when the following code consumed the result unpredictable because it would depend on what junk values were left in the registers. This was originally not a problem since the space of supported functions were tightly packed, but someone added a new function with a gap without adjusting this behavior. This change makes CPUID zero out RAX, RBX, RCX, and RDX when it fails. That should be more predictable and cause less flakey failures. Change-Id: If6ffb17c2969d34aff1600c0ffc32333d0b9be44 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20168 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-13sim: Add a hook Clocked objects can implement for frequency changes.Gabe Black
This hook will let them implement whatever additional behavior is necessary for when the clock changes. An alternative design for this might have made the "update" function virtual, and required anyone overriding it to call into the base class. I think that would be an inferior design for two reasons. First, the subclass author might forget to call update. Second, while it might *seem* like this would have some performance benefit since you wouldn't call into the virtual function and then call update, incurring the function call overhead twice, you're going to call into update once regardless, and then you're either going to call the virtual funciton which does nothing (the norm) or does something. In either case you call the same functions the same number of times. There may be a slight penalty in code size since the call to update may be inlined in the call sights before the virtual function, and there will almost certainly be more of those than there would be implementations of the virtual function, but that should be negligable when compared to gem5's size as a whole. Change-Id: Id25a5359f2b1f7e42c6d1dcbc70a37d3ce092d38 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20089 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-08-13sim: Clean up some mild style bugs in clocked_object.hh.Gabe Black
Clean up some formatting, and also remove redundant inline keywords. A function defined in place in a class definition is already automatically inline. Change-Id: Iaad3a8dda6498c6a6068c2aabc9d6eb11f3d2eb2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20088 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-13mem-ruby: Use check_on_cache_probe on MIPouya Fotouhi
This change uses check_on_cache_probe statement to check if the cacheline subject to eviction is locked in MI. Change-Id: I276822e987e52f7682ff30f55880f295b6af023d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19888 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-08-13mem-ruby: Use check_on_cache_probe on MOESI hammerPouya Fotouhi
This change uses check_on_cache_probe statement to check if the cacheline subject to eviction is locked in MOESI hammer. Change-Id: I2c43f22aba5af3a57e54b1c435e5d3fbba86d1d5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19891 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-08-13mem-ruby: Use check_on_cache_probe on MOESI CMPPouya Fotouhi
This change uses check_on_cache_probe statement to check if the cacheline subject to eviction is locked in MOESI CMP. Change-Id: I3a8879e10ebd94ef68194836475e656761fed62c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19908 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-08-13mem-ruby: Use check_on_cache_probe on MOESIPouya Fotouhi
This change uses check_on_cache_probe statement to check if the cacheline subject to eviction is locked in MOESI. Change-Id: Ie650ccdc15bb41b4088e534975b662408aaccf24 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19890 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-08-12arch-arm: Added LD/ST<op> atomic instruction family and SWP instrsJordi Vaquero
Adding LD/ST/SWP family of instructions, LD/ST include a set of operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN This commit includes: + Instruction decode + Instruction functional code + New set of skeletons for Ex/Com/Ini/Constructor and declaration. Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19812 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-08-12mem-ruby: Use check_on_cache_probe to protect locked lines from evictionPouya Fotouhi
This change uses check_on_cache_probe statement to check if the cacheline subject to eviction is locked in MESI Three Level. Change-Id: Ib0de54aa067c7603db1f7321cc4825b123b641ac Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19868 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-12mem-ruby: Use check_on_cache_probe to protect locked lines from evictionPouya Fotouhi
This change uses check_on_cache_probe statement to check if the cacheline subject to eviction is locked in MESI Two Level. Other protocols should be updated accordingly. Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Change-Id: Idcdbc8ee528eb5e4e2f8d56a268a3a92eadd95b1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16809 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-19 12:00:41 +0000