Age | Commit message (Collapse) | Author |
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src/arch/alpha/predecoder.hh:
src/arch/sparc/predecoder.hh:
Put in a missing include
src/cpu/exetrace.cc:
Convert the legion lockstep stuff from makeExtMI to the predecoder object.
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extra : convert_revision : 91bad4466f8db1447fff8608fa46a5f236dc3a89
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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extra : convert_revision : 3246c58850586b880641638bedb1f0025d0ef491
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a conversion constructor because it caused ambiguous conversions when setting the pointer to NULL.
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extra : convert_revision : ce9ecfc03a47642d105f2378208bbe923d6b765b
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This isn't necessary since they don't use the extended fields, but it's more consistent and more correct.
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extra : convert_revision : afd4f408122ad5e497012eb9744d6bce66a1de37
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into pb15.local:/Users/ali/work/m5.newmem
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extra : convert_revision : 0aa2fadf8978ae30ebe4fde03c525e6b9115117a
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src/arch/x86/predecoder.cc:
File for the x86 predecoder process function.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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extra : convert_revision : cf2cc07f18b877f980e2d1fc83916f7849d9c7d9
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 6a75fa02391c4c65063c5412a568705bb1dd892b
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support enough functionality make the driver think
the device is there, and in good working order.
src/dev/SConscript:
add intel gbe to the dev SCons file
src/dev/i8254xGBe.cc:
src/dev/i8254xGBe.hh:
src/dev/i8254xGBe_defs.hh:
use new manner of registers and implement all device registers that are touched through boot and ifup
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extra : convert_revision : b1a1767f0fd31cd371e432cb48ac9a2e9f9291b5
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extra : convert_revision : 9db0bc2420ceb5828a79881fa0b420a2d5e5f358
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byte opcodes.
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extra : convert_revision : 4c79bff2592a668e1154916875f019ecafe67022
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extra : convert_revision : 4a66d04404beee9656e3e33089afcec10d7ee5ff
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
src/arch/mips/utility.hh:
src/arch/x86/SConscript:
Hand merge
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extra : convert_revision : 0ba457aab52bf6ffc9191fd1fe1006ca7704b5b0
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adding predecoding functionality to x86.
src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
Make the predecoder an object with it's own switched header file.
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extra : convert_revision : 77206e29089130e86b97164c30022a062699ba86
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extra : convert_revision : 3702b4bd038a59bff823c3b428fdfbaabc9715df
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
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extra : convert_revision : 61eca737296a5ce839d3b97f047b4fda062cb899
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Removed the getOpcode function from StaticInst which only made sense for Alpha.
Started implementing the x86 predecoder.
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extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
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src/arch/sparc/ua2005.cc:
fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to
check if were suspended and interrupt at the guess time
src/base/traceflags.py:
add trace flag for Iob
src/cpu/simple/base.cc:
Use Quisce instead of IPI trace flag
src/dev/sparc/iob.cc:
add some Dprintfs
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extra : convert_revision : 72e18fcc750ad1e4b2bb67b19b354eaffc6af6d5
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : db68adffdf4ae12637eba7c03d53aca997b30291
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extra : convert_revision : 5366be897d1193cf9e93b1fcd0689d19783f73a8
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head
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extra : convert_revision : 7d7380a6565cff32470bddadb0158fad897a5cf5
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new version of gdb to work and it causes at least mine to segfault
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extra : convert_revision : 5e4c2ec753372fd0569734d3ddb0c8690409ca16
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extra : convert_revision : 405f10f14f2f6666a7bef01bfb0cf90ff14cef24
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extra : convert_revision : 32d1b23200752fe5fcdcbafb586f50bbe6db3bf3
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head
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extra : convert_revision : 8651b2878853c5a6cb15f60ab92cf39d3bc30a07
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src/cpu/memtest/memtest.cc:
Add the [] to a delete to make it work correctly
src/mem/cache/cache_impl.hh:
Fix one of the memory leaks
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extra : convert_revision : 64c7465c68a084efe38a62419205518b24d852a7
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on uninitialised value(s), in the stats package
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extra : convert_revision : d3a508fc98df4eb8160a211a306be6ab241a4ce8
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : c6fbe09348b606b94bbb35f911dea94353f076f9
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src/arch/sparc/miscregfile.cc:
this code should be in readFSreg
src/arch/sparc/ua2005.cc:
move code froh miscregfile to ua2005.cc
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extra : convert_revision : fa450b04ad73ab6f6e25d66fa0368054263f09f9
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extra : convert_revision : 67e92b166599bd20b7ce90d073f2fd7502f810ec
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floating point condition codes with prediction.
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extra : convert_revision : 812950e92b7e0f34f370a1472c20f52e3ef214b1
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
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extra : convert_revision : 725999a0a5bde6e065bad87b42e973c5c627c69f
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extra : convert_revision : 368d1c57a46fd5ca15461cb5ee8e05fd1e080daa
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automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.
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extra : convert_revision : 103f6b490d2eb224436688c89cdc015211c4fd30
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace-test
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extra : convert_revision : dc02bb6b4e5cc7f0260da80a71b9713f75566a29
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
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extra : convert_revision : 6a8749be327bf2be888850060ae0427f0c943439
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extra : convert_revision : 1fc88b499334bb4ba44375347d0062843587b6cf
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace-test
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extra : convert_revision : df36efd84d938e0e402648b85b3732ed786aaa29
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extra : convert_revision : 8bfa5e9408d1ead0197aab5078c248876f90ea7a
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place where it doesn't access freed memory.
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extra : convert_revision : 4d9023f6193004a3e9cbeebd3721bccb50b2aab0
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
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extra : convert_revision : 82a956ffc1bedb2c0d05c4ea3469f843f559a475
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that for us. This should be contained in the scope of the function and not leak elsewhere.
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extra : convert_revision : 0bb0e1457011505a99a871c443bc45f4365e9c7e
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bit syscall table into it's own file. Corrected problems with the stat structure. These should be tested on 64 bit x86 and SPARC machines.
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extra : convert_revision : 5d9fe19e031b92e111069c6b89c3dbeb29975b8a
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 5804298706ac0f04fbe491326af71ce9ab74425a
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src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/arch/x86/utility.hh:
add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi
src/arch/sparc/isa/decoder.isa:
handle writable bits of strandstatus register in miscregfile
src/arch/sparc/miscregfile.hh:
some constants for the strand status register
src/arch/sparc/ua2005.cc:
properly implement the strand status register
src/dev/sparc/iob.cc:
implement ipi generation properly
src/sim/system.cc:
call into the ISA to start the CPU (or not)
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extra : convert_revision : 0003b2032337d8a031a9fc044da726dbb2a9e36f
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1. Make sure connectMemPorts() only gets called when the CPU's peer gets changed. This is done by making setPeer() virtual, and overriding it in the CPU's ports. When it gets called on a CPU's port (dcache specifically), it calls the normal setPeer() function, and also connectMemPorts().
2. Consolidate redundant code that handles switching in a CPU.
src/cpu/base.cc:
Move common code of switching over peers to base CPU.
src/cpu/base.hh:
Move common code of switching over peers to BaseCPU.
src/cpu/o3/cpu.cc:
Add in function that updates thread context's ports.
Also use updated function to takeOverFrom() in BaseCPU. This gets rid of some repeated code.
src/cpu/o3/cpu.hh:
Include function to update thread context's memory ports.
src/cpu/o3/lsq.hh:
Add function to dcache port that will update the memory ports upon getting a new peer.
Also include a function that will tell the CPU to update those memory ports.
src/cpu/o3/lsq_impl.hh:
Add function that will update the memory ports upon getting a new peer.
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Add function that will update thread context's memory ports upon getting a new peer.
Also use the new BaseCPU's take over from function.
src/cpu/simple/atomic.hh:
Add in function (and dcache port) that will allow the dcache to update memory ports when it gets assigned a new peer.
src/cpu/simple/timing.hh:
Add function that will update thread context's memory ports upon getting a new peer.
src/mem/port.hh:
Make setPeer virtual so that other classes can override it.
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extra : convert_revision : 2050f1241dd2e83875d281cfc5ad5c6c8705fdaf
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