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AgeCommit message (Expand)Author
2019-09-02stats: Add support for listing available formatsAndreas Sandberg
2019-08-30arm,kvm: Fix python imports from global namespaceGiacomo Travaglini
2019-08-29mem-cache: Use SatCounter for RRPVDaniel R. Carvalho
2019-08-29base: Add function to saturate SatCounterDaniel R. Carvalho
2019-08-29stats: Add beta support for HDF5 stat dumpsAndreas Sandberg
2019-08-29mem: Convert CommMonitor to the new stat frameworkAndreas Sandberg
2019-08-29cpu: Convert traffic gen to use new statsAndreas Sandberg
2019-08-29stats: Add support for partial stat dumpsAndreas Sandberg
2019-08-29stats: Add support for hierarchical statsAndreas Sandberg
2019-08-28mem-ruby: Define BloomFilter namespaceDaniel R. Carvalho
2019-08-28mem-ruby: Make H3 inherit from MultiBitSelBloomFilterDaniel R. Carvalho
2019-08-28mem-ruby: Finish implementing BloomFilter mergeDaniel R. Carvalho
2019-08-28mem-ruby: Remove NonCountingBloomFilterDaniel R. Carvalho
2019-08-28mem-ruby: Make MultiGrainBloomFilter genericDaniel R. Carvalho
2019-08-28mem-ruby: Parameterize xor bits in BlockBloomFilterDaniel R. Carvalho
2019-08-28cpu: Make get(Data|Inst)Port return a Port and not a MasterPort.Gabe Black
2019-08-28cpu, mem: Add new getSendFunctional method to the base CPU.Gabe Black
2019-08-28mem: Make PortProxy use a delegate for a sendFunctional function.Gabe Black
2019-08-28cpu: Move the instruction port into o3's fetch stage.Gabe Black
2019-08-28cpu: Move O3's data port into the LSQ.Gabe Black
2019-08-28mem: Eliminate the Base(Slave|Master)Port classes.Gabe Black
2019-08-27cpu, dev, mem: Use the new Port methods.Gabe Black
2019-08-27sim: Add a << overload for the Port class which prints its name.Gabe Black
2019-08-27sim: Add a takeOverFrom method to the base Port class.Gabe Black
2019-08-27mem, sim, systemc: Reorganize Port and co.s bind, unbind slightly.Gabe Black
2019-08-26dev-arm: Fix GICv3 ITS indexing errorGiacomo Travaglini
2019-08-26dev-arm: Fix GITS_BASER initialization/accessGiacomo Travaglini
2019-08-23arch-riscv: fix GDB register cacheAlec Roelke
2019-08-23mem: Put gem5 protocols in their own directory.Gabe Black
2019-08-23mem: Move ruby protocols into a directory called ruby_protocol.Gabe Black
2019-08-23mem: Split the various protocols out of the gem5 master/slave ports.Gabe Black
2019-08-22mem-ruby: fix build with PROTOCOL=MOESI_hammerCiro Santilli
2019-08-22dev-arm: Start using GITS_CTLR.quiescent bitGiacomo Travaglini
2019-08-22dev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR/BASER)Giacomo Travaglini
2019-08-22dev-arm,system-arm: missing GICv3 ranges propertyAdrian Herrera
2019-08-21arch-riscv: Update register fileYifei Liu
2019-08-21arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0Ciro Santilli
2019-08-21base: assert that stats bucket size is greater than 0Ciro Santilli
2019-08-21arch-arm: Fix implicit fallthrough build errorsChun-Chen TK Hsu
2019-08-20dev-arm: Add redistributor-stride property to GICv3Giacomo Travaglini
2019-08-20arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currELGiacomo Travaglini
2019-08-20arch-arm: Replace direct use cpsr.el with currEL helperGiacomo Travaglini
2019-08-20arch-arm: Overload currEL helper with CPSR argumentGiacomo Travaglini
2019-08-20arch-arm: Rewrite the currEL helper method to use opModeToELGiacomo Travaglini
2019-08-20dev-arm: Add GITS_PIDR2 register to the ITS memory mapGiacomo Travaglini
2019-08-20dev-arm: Add Gicv3Distributor members for GICv3 GICD_PIDRxGiacomo Travaglini
2019-08-19mem-ruby, arch-hsail: Removed hit latency from VIPERCoalescerPablo Prieto
2019-08-16x86: Stop CPUID from claiming we support xsave.Gabe Black
2019-08-15x86: Make unsuccessful CPUID instructions zero the result.Gabe Black
2019-08-13sim: Add a hook Clocked objects can implement for frequency changes.Gabe Black
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