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AgeCommit message (Expand)Author
2017-11-28scons: Build GTests in the directory they're declared.Gabe Black
2017-11-28tests: Reimplement the bituniontest as a googletest.Gabe Black
2017-11-28scons: Add in a new type of unit test called GTest.Gabe Black
2017-11-28scons: Minor cleanup of how partial linking is handled in makeEnv.Gabe Black
2017-11-28arch-riscv: Move static_inst into a directoryAlec Roelke
2017-11-27tests: Build the input file into the initest unit test.Gabe Black
2017-11-27scons: Break make_obj into make_static and make_shared functions.Gabe Black
2017-11-27scons: Remove the extra_deps option from the helper function make_obj.Gabe Black
2017-11-27scons: Get rid of a flag which makes Werror optional.Gabe Black
2017-11-27scons: Move some compiler flag setting code to the SConstruct.Gabe Black
2017-11-27scons: Get rid of SourceFile's done function.Gabe Black
2017-11-27scons: Switch from "guards" to "tags" on source files.Gabe Black
2017-11-22tests: Resurrect initest input file(s).Gabe Black
2017-11-22tests: Fix the stats unit test.Gabe Black
2017-11-22arch-arm: Add support for the brk instructionAndreas Sandberg
2017-11-22arch-arm: HVC instruction undefined in secure EL1Giacomo Travaglini
2017-11-22arch-riscv: Add missing system callsAlec Roelke
2017-11-22sim-se: Add default to SyscallDesc constructorAlec Roelke
2017-11-22sparc: Move integer StaticInst base classes out of the ISA desc.Gabe Black
2017-11-22sparc: Move the mem base classes out of the ISA description.Gabe Black
2017-11-22sparc: Move the microop/macroop base classes out of the ISA desc.Gabe Black
2017-11-22sparc: Return debug faults from unimplemented instructions.Gabe Black
2017-11-22sparc: Pull the unimplemented formats out of the ISA description.Gabe Black
2017-11-22sparc: Pull the "Uknown" StaticInst class out of the ISA description.Gabe Black
2017-11-22sparc: Pull most of the Nop format out of the ISA description.Gabe Black
2017-11-22sparc: Pull more StaticInst base classes out of the ISA desc.Gabe Black
2017-11-22sparc: Pull flat static instruction classes out of the ISA.Gabe Black
2017-11-21arch-arm: ArmPMU refactorJose Marinho
2017-11-21arch-arm: Do not increment PMU cycle event in WFI/WFEJose Marinho
2017-11-21cpu, cpu, sim: move Cycle probe updateJose Marinho
2017-11-21sim: Fix need to save address space info during serialization.Austin Harris
2017-11-21arch-arm: Fix MCR/MRC disassembleGiacomo Travaglini
2017-11-21arch-arm: Fix MSR/MRS disassembleGiacomo Travaglini
2017-11-21cpu-o3: Prevent cpu from suspending if it is already drainingNikos Nikoleris
2017-11-20arch-arm: Ensure counters keep events on checkpoint resumeJose Marinho
2017-11-20cpu: Make automatic transition to OFF optionalJose Marinho
2017-11-20pwr: Adds logic to enter power gating for the cpu modelAnouk Van Laer
2017-11-20sparc: Pull StaticInst base classes out of the ISA description.Gabe Black
2017-11-20dev: Fix the SPARC and X86 platform devices.Gabe Black
2017-11-19tests: Fix compilation of cprinftest.Gabe Black
2017-11-17sim: Implement load_addr_mask auto-calculationGeoffrey Blake
2017-11-16sim: ScopedMigration does nothing if both eqs are the sameTiago Muck
2017-11-16ext, mem: Pull DRAMPower SHA 90d6290 and rebaseRadhika Jagtap
2017-11-16pwr: Enable multiple power models per componentDavid Guillen Fandos
2017-11-16arch, arm: Print value being ignored on DummyISA writeSean McGoogan
2017-11-16sim: Clocked object debug message updated for clarityTiago Muck
2017-11-16sim: Add an option to load additional kernel objectsAndreas Sandberg
2017-11-15arch-arm: Dsb instruction shouldn't flush the pipelineGiacomo Travaglini
2017-11-15arch-arm: Writes to DCCMVAC shouldn't flush pipelineGiacomo Travaglini
2017-11-15arch-arm: Removing FlushPipe fault, using SquashAfterGiacomo Travaglini