summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2019-05-20sparc: Add an object file loader for linux and solaris.Gabe Black
Change-Id: I76bcbc06714f7d538f03a8311994a868de3640f1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18629 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-20riscv: Add an object file loader for linux.Gabe Black
Change-Id: I3accca91cc4e02fa8e3a1169590cbe6696cf05e2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18628 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-05-20power: Add an object file loader for linux.Gabe Black
Change-Id: I64ce81e98a6dc96754554d0fdcd7d16b8a2752d4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18587 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>
2019-05-20mips: Add an object file loader for linux.Gabe Black
Change-Id: Icae6430a210076117cf2ceadce52d6efbe58a5f3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18586 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-18arm: Add an object file loader for linux and freebsd.Gabe Black
Change-Id: Ie5fd187a4897aa608ffc12278b23d3ee8c0f323c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18585 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-18alpha: Add an object file loader for linux.Gabe Black
Change-Id: I91c4019567bdf74b2517fda597121a6ad107cb86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18584 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-18base: Add a type for keeping track of object file loaders.Gabe Black
This avoids having a big pile of #if-s in sim/process.cc and allows dynamically adding new types of object file loaders which might recognize new arch/OS combinations. Change-Id: Ie3b9c1aa2974d30a61afc4fcc529ffd6a74d43e0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18583 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-18arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.Gabe Black
This code will be preserved through version control, but otherwise creates clutter and will rot in place since it's never compiled. Change-Id: Id265f6deac445116843956ea5cf1210d8127274e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-17arch-arm: implement VMINNM and VMAXNM scalar versionCiro Santilli
ARMv8.2 16-bit versions have not yet been implemented, but a placeholders were created for them. Refactor the nearby decoding tree to closely match the ARM spec A32 decode table. That piece of the tree can also be called from thumb which decodes it in the same way, although the thumb decode table has a different terminology The old code didn't match neither A32 or T32 terminologies, so it is better to at least match one of them to help verify correctness. Change-Id: Iabbbca2932557cf6c98ce36690c385c3ddf39ed8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18690 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-17arch-arm: implement VMINNM and VMAXNM SIMD versionCiro Santilli
This instruction is backported from aarch64. In order to use the existing fplibMinNum backend, we first move VMIN and VPMIN to use fplib. Adding VMINNM is then trivial. Change-Id: I404daabeb6079f60e51a648a06d5b3e54f1c24a9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18689 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-17arch-arm: rename operands to match spec in isa/formats/fp.isaCiro Santilli
Matches ARM DDI 0487D.a decoding tables. Change-Id: I48338ef956a04308d55d1022229ebe0962a8fe5d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18688 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-14mem-ruby: MOESI_CMP_dir cleanupTiago Muck
Removed unused states and actions Change-Id: I3dc684c78d4b92d219e71522ddb706a13f9874d1 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18415 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: John Alsop <johnathan.alsop@amd.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Cache latencies for MOESI_CMP_dirTiago Muck
Modified both L1 and L2 controllers to take into account the cache latency parameters. Default values in the configuration script updated as well. Change-Id: I72bb8dd29ee0b02da06e1addf13b266fe4d1e979 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18414 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Hit latencies defined by the controllersTiago Muck
Removed the icache/dcache hit latency parameters from the Sequencer. They were replaced by the mandatory queue enqueue latency that is now defined by the top-level cache controller. By default, the latency is defined by the mandatory_queue_latency parameter. When the latency depends on specific protocol states or on the request type, the protocol may override the mandatoryQueueLatency function. Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18413 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Do not change blocked msg enqueue infoTiago Muck
Updating the message counter and enqueue times when adding blocked messages back to the queue does not make a lot of sense since these messages are not new arrivals. More importantly, this may lead to starvation. See the scenario below: 1) Request A for a blocked line X arrives 2) A is handled; X is blocked so A is stalled 3) Request B for X arrives; Reponse for X arrives 4) Response is handled; X unblocked; A added back to the request queue 5) B is handled ahead of A (since A's arrival was updated); X may become blocked again If new requests keep comming for X, A may will be stalled forever. Change-Id: Icad79f3f716a870e91cb3455437b8b3c35f130ac Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18412 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Unique ranks for MOESI_CMP_dir in portsTiago Muck
Setting different values for the rank parameter for all inputs ports. If left unset, it defaults to 0. This may cause issues since the rank is used as an index in the controller's list of stalled buffers. Change-Id: Ie8ff660b7450df959292311040aebf802657efcf Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18411 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Change MOESI_CMP_Dir L2 addressingTiago Muck
L1 controller selects the L2 to message based on the assigned address ranges instead of explicitly interleaving bits in the L1 controller. This simplifies the L1 controller implementation a bit and allows for more flexibility when changing the address->controller mapping. Change-Id: Ie67999bb977566939432a5045f65dbd2da81816a Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18410 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Fix MOESI_CMP_dir debug msgTiago Muck
Change-Id: I3fd32bd2e81dbf9a8ea49a43727564b8a9d64767 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18409 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Prevent response stalls on MOESI_CMP_directoryTiago Muck
When a message triggers a transition that has actions which allocate TBEs, the generated code automatically includes a check for the TBETable size before executing any action. If the table is full, the transition returns TransitionResult_ResourceStall and no more messages from the buffer are handled (until the next cycle). This behavior may lead to deadlocks in the MOESI_CMP_directory protocol since events triggered by the response queue may allocate TBEs (e.g. L2 replacements triggered by the response queue). If the table is full, the queue is stalled preventing other responses from freeing TBEs. This patch fixes this by handling WRITEBACK_DIRTY_DATA/CLEAN_DATA messages as requests and WB_ACK/WB_NACK as responses. All controllers are changed to work with the new types. With this fix, responses are always handled first in all controllers, and no response triggers TBE allocations. Change-Id: I377c0ec4f06d528e9f0541daf3dcc621184f2524 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18408 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: John Alsop <johnathan.alsop@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14arch-arm: Do not check MustBeOne flag for TLB requests from the prefetcherJavier Bueno
Allow TLB requests generated from prefetchers to override the MustBeOne arch flag. This allows the prefetchers to issue requests without having to know architecutre-specific flags. Change-Id: Id83e0c93f3d1a614da11c4f344ab4dc594423672 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18768 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-14Revert "cpu: fix how a thread starts up in MinorCPU"Giacomo Travaglini
This reverts commit 02dafc5498750d9734ba8f2a1608a846f90b71d1. The commit was part of a patchset which broke MinorCPU regressions (switcheroo) Change-Id: I0a8098fc71abe5838014e587dbe372b258d8aa9f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18604 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-14Revert "cpu: stop scheduling suspended threads in MinorCPU"Giacomo Travaglini
This reverts commit 6a6668bbc4b038b98eb3ee64ffb034719316afd9. The commit was part of a patchset which broke MinorCPU regressions (switcheroo) Change-Id: I3c16a6478ba44b9d27cdd3d64a710a356999df05 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18603 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-14Revert "cpu: fix branching when thread is suspended in MinorCPU"Giacomo Travaglini
This reverts commit e437086341712f1435db655b3527ea29b3311f4e. The commit was part of a patchset which broke MinorCPU regressions (switcheroo) Change-Id: Ib8482034c2402008ccfa552325a8eb31e731b619 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18602 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-14mem-cache: Use SatCounter for prefetchersDaniel
Many prefetchers re-implement saturating counters with ints. Make them use SatCounters instead. Added missing operators and constructors to SatCounter for that to be possible and their respective tests. Change-Id: I36f10c89c27c9b3d1bf461e9ea546920f6ebb888 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17995 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14base: Add operators to SatCounterDaniel
Add shift, add and subtract assignment operators, as well as copy and move constructor and assignments to SatCounter, so that it they can be used by the prefetchers. Also add extra useful functions to calculate saturation oercentile so that the instantiator does not need to be aware of the counter's maximum value. Change-Id: I61d0cb28c8375b9d2774a39011e4a0aa6fe9ccb7 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17996 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14base: Add GTest to SatCounterDaniel
Add a GTest to the SatCounter class. Change-Id: Iaf1b18db9fe8d7fe32e0e40c7947dcd1fd6cc33b Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17994 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-05-14base: Move SatCounter to base directoryDaniel
Saturating counters are used by many objects, not only the cpu predictors. Therefore, move the class to the base folder so that it can be more easily used. Change-Id: I26f799324bdd8720ab8834c72a2002149cee777c Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17993 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-05-14cpu: Revamp saturating countersDaniel
Revamp the SatCounter class, improving comments, implementing increment, decrement and read operators to solve an old todo, and adding missing error checking. Change-Id: Ia057c423c90652ebd966b6b91a3471b17800f933 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17992 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-13cpu: Make the indirect predictor into a SimObjectJairo Balart
Change-Id: Ice6549773def7d3e944fae450d4a079bc351e2ba Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15319 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-12mem-ruby: Replace string parameter in MultiBitSelBloomFilterDaniel R. Carvalho
Replace string parameter from MultiBitSelBloomFilter's constructor by their tokenized counterparts. Change-Id: I2e3db109dc4814fa0e9c13259f1136a6c4083092 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18728 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-11arch-arm: Add initial support for SVE contiguous loads/storesGiacomo Gabrielli
Thanks to Pau Cabre and Adria Armejach Sanosa for their contribution of bugfixes. Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13519 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-05-11cpu,mem: Add support for partial loads/stores and wide mem. accessesGiacomo Gabrielli
This changeset adds support for partial (or masked) loads/stores, i.e. loads/stores that can disable accesses to individual bytes within the target address range. In addition, this changeset extends the code to crack memory accesses across most CPU models (TimingSimpleCPU still TBD), so that arbitrarily wide memory accesses are supported. These changes are required for supporting ISAs with wide vectors. Additional authors: - Gabor Dozsa <gabor.dozsa@arm.com> - Tiago Muck <tiago.muck@arm.com> Change-Id: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13518 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-11cpu: Add a memory access predicateGiacomo Gabrielli
This changeset introduces a new predicate to guard memory accesses. The most immediate use for this is to allow proper handling of predicated-false vector contiguous loads and predicated-false micro-ops of vector gather loads (added in separate changesets). Change-Id: Ice6894fe150faec2f2f7ab796a00c99ac843810a Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17991 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bradley Wang <radwang@ucdavis.edu> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-09mem-ruby: Fix MOESI_CMP_directory blocked line handlingTiago Muck
Using recycle in the L2 controllers to put messages back into the buffer may lead to starvation when there are many L1 requests for the same line. This can easily trigger the deadlock detection mechanism in configurations with many cores (16+). Replacing recycle by stall_and_wait for L1 requests avoids this issue. wakeUpBuffers calls were added to all transitions from transient to stable states. Change-Id: I28b8aeacc48919ccf38e69653cd9205a4153514b Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17568 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-08mem-cache: Remove writebacks packet listDaniel R. Carvalho
Previously all atomic writebacks concerned a single block, therefore, when a block was evicted, no other block would be pending eviction. With sector tags (and compression), however, a single replacement can generate many evictions. This can cause problems, since a writeback that evicts a block may evict blocks in the lower cache. If one of these conflict with one of the blocks pending eviction in the higher level, the snoop must inform it to the lower level. Since atomic mode does not have a writebuffer, this kind of conflict wouldn't be noticed. Therefore, instead of evicting multiple blocks at once, we do it one by one. Change-Id: I2fc2f9eb0f26248ddf91adbe987d158f5a2e592b Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18209 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Handle data expansionDaniel R. Carvalho
When a block in compressed form is overwriten, it may change its size. If the new compressed size is bigger, and the total size becomes bigger than the block size, one or more blocks will have to be evicted. This is called data expansion, or fat writes. This change assumes that a first level cache cannot have a compressor, since otherwise data expansion should have been handled for atomic operations and writes. As such, data expansions should only be seen on writebacks. As writebacks are forwarded to the next level when failed, there should be no data expansions when servicing misses either. This patch adds the functionality to handle data expansions by evicting the co-allocated blocks to make room for an expanded block. Change-Id: I0bd77bf6446bfae336889940b2f75d6f0c87e533 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12087 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-08mem-cache: Add co-allocation function to compressed tagsDaniel R. Carvalho
Implement a co-allocation function in compressed tags, so that compressed blocks can be co-allocated in a superblock. Co-allocation is possible when compression ratio (CR) blocks that share a superblock tag can be compressed to up to (100/CR)% of their size. Change-Id: I937cc1fcbb488e70309cb5478c12db65f1b4b23f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11411 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Add compression and decompression callsDaniel R. Carvalho
Add a compressor to the base cache class and compress within block allocation and decompress on writebacks. This change does not implement data expansion (fat writes) yet, nor it adds the compression latency to the block write time. Change-Id: Ie36db65f7487c9b05ec4aedebc2c7651b4cb4821 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11410 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Create BDI CompressorDaniel R. Carvalho
Implement Base-Delta-Immediate compression, as described in 'Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches' Change-Id: I7980c340ab53a086b748f4b2108de4adc775fac8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11412 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Add compression statsDaniel R. Carvalho
Add compression statistics to the compressors. It tracks the number of blocks that can fit into a certain power of two size, and the number of decompressions. For example, if a block is compressed to 100 bits, it will belong to the 128-bits compression size. Although it could also fit bigger sizes, they are not taken into account for the stats (i.e., the 100-bit compression will fit only the 128-bits size, not 256 or higher). We save stats for compressions that fail (i.e., compressed size is bigger than original cache line size). Change-Id: Idab71a40a660e33259908ccd880e42a880b5ee06 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11103 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Create cache compressorDaniel R. Carvalho
Create basic template for cache compressors. A basic compressor must implement a compression and a decompression method. Change-Id: I83dc4d2b8d2bc5ed9f760c938edfa4ebdd6b8583 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11100 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Add block size to findVictimDaniel R. Carvalho
Add block size to findVictim. For standard caches it will not be used. Compressed caches, however, need to know the size of the compressed block to decide whether a block is co-allocatable or not. Change-Id: Id07f79763687b29f75d707c080fa9bd978a408aa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11198 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Mohammad Seyedzadeh <sm.seyedzade@gmail.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Add compression data to CompressionBlkDaniel R. Carvalho
Add a compression bit, decompression latency and compressed block size and their respective getters and setters. Change-Id: Ia9d8656552d60e8d4e85fe5379dd75fc5adb0abe Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11102 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Create CacheComp debug flagDaniel R. Carvalho
Create a debug flag for cache compression. Change-Id: Id4b8e86d658d3aa550906ee0f8da3b54f4cdab7d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11104 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-08mem-cache: Stub compression frameworkDaniel R. Carvalho
Create a stub of a compression framework where we can have multiple data blocks per tag entry. Only consecutive blocks can share a tag as of now. For each tag entry there can be multiple data blocks. We have the same number of tags a conventional cache would have, but we instantiate the maximum number of data blocks (according to the compression ratio) per tag, to virtually implement compression without increasing the complexity of the simulator. Change-Id: I549940c7afb2f744ab293ff8bb283967e7551a11 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10763 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-07x86: Mark translation as delayed in case of a hw page table walkGabor Dozsa
This information is used by the LSQ in the O3 cpu (since commit "51becd2... cpu-o3: O3 LSQ Generalisation") Change-Id: I35fe7e2f8428641d863af0e79e28b0b259fb0b00 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18508 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-06sim-se: correct statfs inclusion on !linux hostAndrea Mondelli
- Added missing header - Fixed typo on __linux__ macro conditional - s/ifdef/if defined/g for consistency Change-Id: I83b69856e5ec8b23b707642c0e14216cf62db31e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18668 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-04arch-riscv: Implement MHARTID CSRAlec Roelke
This patch implements the MHARTID CSR by intercepting attempts to access it, similar to the way accesses to the performance counters are intercepted, to return the thread's context ID. Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16988 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-03sim-se: fix a few bugs/warns from GCC 6Joe Gross
Change-Id: Ib2ad860324fd234b23262d141be3e82628ff61f0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12126 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-05-03sim-se: add eventfd system callBrandon Potter
Change-Id: I7aeb4fe808d0c8f2fb8041e3662d330d8458f09c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12125 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 16:35:04 +0000