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AgeCommit message (Expand)Author
2016-01-17sim: fix redundant --debug-start help stringSteve Reinhardt
2016-01-17cpu. arch: add initiateMemRead() to ExecContext interfaceSteve Reinhardt
2016-01-17cpu: remove unnecessary data ptr from O3 internal read() funcsSteve Reinhardt
2016-01-17arch: don't call *Timing functions from *Atomic versionsSteve Reinhardt
2016-01-17arch: get rid of unused LargestRead typedefSteve Reinhardt
2016-01-17sim: don't ignore SIG_TRAPSteve Reinhardt
2016-01-15dev, arm: Add a platform with support for both aarch32 and aarch64Andreas Sandberg
2016-01-15dev, arm: Add support for automatic PCI interrupt routingAndreas Sandberg
2016-01-11mem: fix bug in packet access endianness changesSteve Reinhardt
2016-01-11scons: Enable -Wextra by defaultAndreas Hansson
2016-01-11ext: Replace gzstream with iostream3 from zlib to avoid LGPLAndreas Hansson
2016-01-07dev: Distributed Ethernet link for distributed gem5 simulationsGabor Dozsa
2016-01-07pseudo inst,util: Add optional key to initparam pseudo instructionGabor Dozsa
2015-12-31mem: add CacheVerbose debug flag, filter noisy DPRINTFsSteve Reinhardt
2015-12-31mem: Do not rely on the NeedsWritable flag for responsesAndreas Hansson
2015-12-31mem: Do not allocate space for packet data if not neededAndreas Hansson
2015-12-31mem: Do not alter cache block state on uncacheable snoopsAndreas Hansson
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
2015-07-20ruby: slicc: have a static MachineTypeTony Gutierrez
2015-07-20ruby: slicc: remove support for single machine, multiple typesTony Gutierrez
2015-12-28mem: Explicitly check MSHR snoops for cases not dealt withAndreas Hansson
2015-12-28mem: Remove unused cache squash functionalityAndreas Hansson
2015-12-28mem: Avoid unecessary checks when creating HardPFReq in cacheAndreas Hansson
2015-12-28mem: Do not use sender state to track forwarded snoops in cacheAndreas Hansson
2015-12-28mem: Fix cache sender state handling and add clarificationAndreas Hansson
2015-12-18arm: remote GDB: rationalize structure of register offsetsBoris Shingarov
2015-12-18sim: Use the old work item behavior by defaultAndreas Sandberg
2015-12-17mem: Fix memory allocation bug in deferred snoop handlingAndreas Hansson
2015-12-14sim: Add an option to forward work items to PythonAndreas Sandberg
2015-07-20mem: add request types for acquire and releaseDavid Hashe
2015-07-20ruby: more flexible ruby tester supportBrad Beckmann
2015-12-10dev: Add missing SConscript in src/dev/i2cAndreas Sandberg
2015-12-10dev: Move storage devices to src/dev/storage/Andreas Sandberg
2015-12-10dev: Move network devices to src/dev/net/Andreas Sandberg
2015-12-10dev: Move i2c functionality to src/dev/i2c/Andreas Sandberg
2015-12-10dev: Move the CopyEngine class to src/dev/pciAndreas Sandberg
2015-12-10dev: Move existing PCI device functionality to src/dev/pciAndreas Sandberg
2015-11-05sim: Disable gzip compression for writefile pseudo instructionSascha Bischoff
2015-09-18dev, arm: Add gem5 extensions to support more than 8 coresKarthik Sangaiah
2015-12-09mem: remove acq/rel cmds from packet and add mem fence reqTony Gutierrez
2015-12-09syscall_emul: don't check host fd when allocating target fdSteve Reinhardt
2015-12-07cpu: Support virtual addr in elastic tracesRadhika Jagtap
2015-12-07cpu: Create record type enum for elastic tracesRadhika Jagtap
2015-12-07cpu: Add TraceCPU to playback elastic tracesRadhika Jagtap
2015-12-07mem: Add instruction sequence number to requestRadhika Jagtap
2015-12-07proto, probe: Add elastic trace probe to o3 cpuRadhika Jagtap
2015-12-07probe: Add probe in Fetch, IEW, Rename and CommitRadhika Jagtap
2015-12-05dev: Rewrite PCI host functionalityAndreas Sandberg
2015-12-04cpu: fix unitialized variable which may cause assertion failurePau Cabre
2015-12-04sim: Get rid of the non-const serialize() methodAndreas Sandberg
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