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AgeCommit message (Expand)Author
2013-09-06ruby: network: convert to gem5 style statsNilay Vaish
2013-09-06ruby: profiler: removes function resourceUsage()Nilay Vaish
2013-09-06ruby: remove undefined message size typeNilay Vaish
2013-09-06ruby: network: removes reset functionalityNilay Vaish
2013-09-06ruby: network: shorten variable namesNilay Vaish
2013-09-06stats: adds a Formula operator for divisionNilay Vaish
2013-09-06ruby: converts sparse memory stats to gem5 styleNilay Vaish
2013-09-05sim: Fix clang warning for unused variableAndreas Hansson
2013-09-04util: Add ini string as tooltip info in dot outputAndreas Hansson
2013-09-04util: Add colours to the dot outputAndreas Hansson
2013-09-04util: Add class name to dot graph and output to svgAndreas Hansson
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-09-04cpu: Move the branch predictor out of the BaseCPUAndreas Hansson
2013-09-04arch: Header clean up for NOISA resurrectionAndreas Hansson
2013-09-04alpha: Move system virtProxy to Alpha onlyAndreas Hansson
2013-09-04scons: Enable build on OSXAndreas Hansson
2013-08-20cpu: Fix timing CPU isDrained comment formattingAndreas Hansson
2013-08-20base: Fix VectorPrint initialisationAndreas Hansson
2013-08-19stats: Cumulative stats updateAndreas Hansson
2013-08-19cpu: Accurately count idle cycles for simple cpuLena Olson
2013-08-19config: Command line support for multi-channel memoryAndreas Hansson
2013-08-19mem: Change AbstractMemory defaults to match the common caseAndreas Hansson
2013-08-19cpu: Fix TrafficGen trace playbackSascha Bischoff
2013-08-19mem: Use STL deque in favour of list for DRAM queuesAndreas Hansson
2013-08-19mem: Perform write merging in the DRAM write queueAndreas Hansson
2013-08-19mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAMAmin Farmahini
2013-08-19cpu: Fix timing CPU drain checkAndreas Hansson
2013-08-19alpha: Check interrupts before quiesceAndreas Hansson
2013-08-19stats: Fix issue when printing 2D vectorsSascha Bischoff
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-08-19mem: Warn instead of panic for tXAW violationAndreas Hansson
2013-08-19mem: Allow disabling of tXAW through a 0 activation limitAndreas Hansson
2013-08-19mem: Add an internal packet queue in SimpleMemoryAndreas Hansson
2013-08-19cpu: Fix a bug in the O3 CPU introduced by the cache line patchAndreas Hansson
2013-08-07ruby: slicc: remove double trigger, continueProcessingNilay Vaish
2013-08-07ruby: slicc: move some code to AbstractControllerNilay Vaish
2013-08-07x86: add tlb checkpointingNilay Vaish
2013-07-19cpu: Remove unused getBranchPred() method from BaseCPUAndreas Sandberg
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-07-18mem: Add cache class destructor to avoid memory leaksXiangyu Dong
2013-07-18sim: Make MaxTick in Python match the one in C++Andreas Hansson
2013-07-15loader: Load weak symbols for function tracingDeyuan Guo
2013-07-15debug : Fixes the issue wherein Debug symbols were not getting dumped into tr...Umesh Bhaskar
2013-07-11dev: make BasicPioDevice take size in constructorSteve Reinhardt
2013-07-11dev: consistently end device classes in 'Device'Steve Reinhardt
2013-07-11dev/arm: get rid of AmbaDev namespaceSteve Reinhardt
2013-07-11devices: make more classes derive from BasicPioDeviceSteve Reinhardt
2013-07-11ruby: removed the very old double trigger hackBrad Beckmann
2013-06-28ruby: append transition comment only when in opt/debugNilay Vaish
2013-06-28ruby: network: remove reconfiguration codeNilay Vaish
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