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AgeCommit message (Expand)Author
2007-08-26Address translation: Make the page table more flexible.Gabe Black
2007-08-26O3 CPU: Remove alignment check from dynamic instruction read/write functions.Gabe Black
2007-08-26X86: Remove x86 code that attempted to fix misaligned accesses.Gabe Black
2007-08-26Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.Gabe Black
2007-08-26Simple CPU: Added code that will split requests that cross block boundaries i...Gabe Black
2007-08-26Simple CPU: Make sure only instructions which complete without faulting are c...Gabe Black
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-08-26SPARC: Make sure unaligned access are caught on cached translations as well.Gabe Black
2007-08-21Merge with head.Gabe Black
2007-08-21o3: Fix for retry ID bug.Kevin Lim
2007-08-18Merge with head.Gabe Black
2007-08-17Ports: Only try to do EthPort stuff in full system.Ali Saidi
2007-08-16PCI: Move PCI Configuration data into devices now that we can inherit paramet...Ali Saidi
2007-08-16Devices: Make EtherInts connect in the same way memory ports currently do.Ali Saidi
2007-08-13SPARC: Make nops have the IsNop flag set.Gabe Black
2007-08-13O3: Set up the predicted npc and nnpc for a fault carrying noop so that it do...Gabe Black
2007-08-13SPARC: Move tlb state into the tlb.Gabe Black
2007-08-13SPARC: Make the spill and fill handlers use the correct ASI, and let No_Fault...Gabe Black
2007-08-13Move the "translate" member functions back into the base o3 class.Gabe Black
2007-08-13python: make the DictImporter's unload() work in any context.Nathan Binkert
2007-08-12MemorySystem: Fix the use of ?: to produce correct results.Ali Saidi
2007-08-08Added fastmem option.Vincentius Robby
2007-08-08alpha: Quick fix for things related to TLB MRU cache.Vincentius Robby
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-08-10Bus: Only call end() on an stl object once in a loopAli Saidi
2007-08-08Port, StaticInst: Revert unnecessary changes.Vincentius Robby
2007-08-08alpha: Make the TLB cache to actually work.Vincentius Robby
2007-08-07Alpha: Fix an off by one error with the tlb caching mechanism.Gabe Black
2007-08-07Merge with head.Gabe Black
2007-08-07X86: Added some missing parenthesis in the condition code calculation function.Gabe Black
2007-08-07X86: Implemented and hooked in SCAS (scan string)Gabe Black
2007-08-07X86: Add a format to handle string instructions which can use the repe and re...Gabe Black
2007-08-07X86: Overhaul of ruflags to get it to work correctly.Gabe Black
2007-08-07X86: Make a microcode branch microop.Gabe Black
2007-08-04Merge with head.Gabe Black
2007-08-04X86: Implement microops and instructions that manipulate the flags register.Gabe Black
2007-08-04X86: Make 64 bit unaligned accesses work as well as the other sizes.Gabe Black
2007-08-04X86: Make the open flags correct.Gabe Black
2007-08-04X86: Make fixed register operands ignore register index extensions from the R...Gabe Black
2007-08-04X86: Implement the cmpxchg instruction.Gabe Black
2007-08-04X86: Start implementing segmentation support.Gabe Black
2007-08-04X86: Create a base enum value for indexing into a region of the miscregs.Gabe Black
2007-08-04X86: Add the arch_prctl system call and fix up some microcoding.Gabe Black
2007-08-04switching: turn on profiling after a switch if there's an eventNathan Binkert
2007-08-04switching: Remove the drain and resume code from the switching code.Nathan Binkert
2007-08-04python: use the enum values in the memory mode changing codeNathan Binkert
2007-08-04swig: %include all of the enums to get all of the definitions.Nathan Binkert
2007-08-04python: provide access to statsNathan Binkert
2007-08-04main: return an an exit code of 1 when we exit due to a python exception.Nathan Binkert
2007-08-04SimpleCPU: Add some DPRINTFsNathan Binkert