summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2014-09-09config: Fix vectorparam command line parsingGeoffrey Blake
2014-09-09cpu: Only iterate over possible threads on the o3 cpuMitch Hayenga
2014-09-09mem: Add accessor function for vaddrMitch Hayenga
2014-09-09sim: Fix resource leak in BaseGlobalEventAndreas Sandberg
2014-09-09misc: Fix a number of unitialised variables and membersAndreas Hansson
2014-09-03dev: seperate legacy io offsets from PCI offsetAli Saidi
2014-09-03arm: Support >2GB of memory for AArch64 systemsAli Saidi
2014-09-03dev, arm: Add support for linux generic pci host driverAli Saidi
2014-09-03config: Add port splicing capability to PortRef classGeoffrey Blake
2014-09-03config: Refactor RealviewEMM to fit into new config systemGeoffrey Blake
2014-09-03base: Use STL C++11 random number generationAndreas Hansson
2014-09-03base: Use the global Mersenne twister throughoutAndreas Hansson
2014-09-03mem: Avoid unecessary retries when bus peer is not readyAndreas Hansson
2014-09-03arm: Make memory ops work on 64bit/128-bit quantitiesMitch Hayenga
2014-06-27mem: write streaming support via WriteInvalidate promotionCurtis Dunham
2014-09-03mem: Fix a bug in the cache port flow controlAndreas Hansson
2014-05-13cpu, mem: Make software prefetches non-blockingCurtis Dunham
2014-05-13mem: Refactor assignment of Packet typesCurtis Dunham
2014-09-03x86: Flag instructions that call suspend as IsQuiesceMitch Hayenga
2014-09-03cpu: Fix o3 drain bugMitch Hayenga
2014-09-03arm: Fix v8 neon latency issue for loads/storesMitch Hayenga
2014-04-29arm: use condition code registers for ARM ISACurtis Dunham
2014-09-03arm: ISA X31 destination register fixAndrew Bardsley
2014-09-03cpu: fix bimodal predictor to use correct global history regDam Sunwoo
2014-09-03arm: Mark v7 cbz instructions as direct branchesMitch Hayenga
2014-09-03cpu: Fix cache blocked load behavior in o3 cpuMitch Hayenga
2014-09-03cpu: Fix o3 quiesce fetch bugMitch Hayenga
2014-09-03cpu: Fix SMT scheduling issue with the O3 cpuMitch Hayenga
2014-09-03cpu: Fix incorrect speculative branch predictor behaviorMitch Hayenga
2014-09-03cpu: Add a fetch queue to the o3 cpuMitch Hayenga
2014-09-03cpu: Fix o3 front-end pipeline interlock behaviorMitch Hayenga
2014-09-03cpu: Change writeback modeling for outstanding instructionsMitch Hayenga
2014-09-03arch: Properly guess OpClass from optional StaticInst flagsMitch Hayenga
2014-09-03cache: Fix handling of LL/SC requests under contentionGeoffrey Blake
2014-05-27arm: support 16kb vm granulesCurtis Dunham
2014-09-03mem: Packet queue clean upAndreas Hansson
2014-09-03dev: Avoid invalid sized reads in PL390 with DPRINTF enabledMitch Hayenga
2014-09-03sim: Fix checkpoint restore for TickedAndrew Bardsley
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
2014-09-03arch: Cleanup unused ISA traits constantsAndreas Hansson
2014-09-03config: Change parsing of Addr so hex values work from scriptsMitch Hayenga
2014-09-03arm: Fix ExtMachInst hash operator underlying typeAndreas Hansson
2014-09-01ruby: remove typedef of Index as int64Nilay Vaish
2014-09-01x86: set op class of two fp instructionsNilay Vaish
2014-09-01ruby: PerfectSwitch: moves code to a per vnet helper functionNilay Vaish
2014-09-01ruby: message buffers: significant changesNilay Vaish
2014-09-01build opts: add MI_example to NULL ISANilay Vaish
2014-09-01mem: change the namespace Message to ProtoMessageNilay Vaish
2014-09-01ruby: slicc: change the way configurable members are specifiedNilay Vaish
2014-09-01ruby: slicc: improve the grammarNilay Vaish
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 16:06:43 +0000