gem5 - gem5

Age	Commit message (Expand)	Author
2014-06-30	mem: DRAMPower trace output	Andreas Hansson
2014-06-30	mem: Add bank and rank indices as fields to the DRAM bank	Andreas Hansson
2014-06-30	mem: Extend DRAM row bits from 16 to 32 for larger densities	Andreas Hansson
2014-06-30	cpu: implement a bi-mode branch predictor	Anthony Gutierrez
2014-06-21	x86: fix table walker assertion	Binh Pham
2014-06-21	o3: make dispatch LSQ full check more selective	Binh Pham
2014-06-21	o3: split load & store queue full cases in rename	Binh Pham
2014-06-10	scons: Bump the compiler version to gcc 4.6 and clang 3.0	Andreas Hansson
2014-06-09	sim: More rigorous clocking comments	Joel Hestness
2014-05-31	style: eliminate equality tests with true and false	Steve Reinhardt
2014-05-23	ruby: slicc: remove unused ids DNUCA*	Nilay Vaish
2014-05-23	ruby: remove old protocol documentation	Nilay Vaish
2014-05-23	ruby: message buffer: drop dequeue_getDelayCycles()	Nilay Vaish
2014-05-23	cpu: o3: remove stat totalCommittedInsts	Nilay Vaish
2014-05-12	syscall emulation: clean up & comment SyscallReturn	Steve Reinhardt
2014-05-09	mem: Update DDR3 and DDR4 based on datasheets	Andreas Hansson
2014-05-09	mem: Add DRAM cycle time	Andreas Hansson
2014-05-09	mem: Simplify DRAM response scheduling	Andreas Hansson
2014-05-09	mem: Add precharge all (PREA) to the DRAM controller	Andreas Hansson
2014-05-09	mem: Remove printing of DRAM params	Andreas Hansson
2014-05-09	mem: Add tRTP to the DRAM controller	Andreas Hansson
2014-05-09	mem: Merge DRAM latency calculation and bank state update	Andreas Hansson
2014-05-09	mem: Add tWR to DRAM activate and precharge constraints	Andreas Hansson
2014-05-09	mem: Merge DRAM page-management calculations	Andreas Hansson
2014-05-09	mem: Add DRAM power states to the controller	Andreas Hansson
2014-05-09	mem: Ensure DRAM refresh respects timings	Andreas Hansson
2014-05-09	mem: Make DRAM read/write switching less conservative	Andreas Hansson
2014-04-17	arm: Make sure UndefinedInstructions are properly initialized	Ali Saidi
2014-04-17	arm: allow DC instructions by default so SE mode works	Ali Saidi
2014-04-17	sim, arm: implement more of the at variety syscalls	Ali Saidi
2014-05-09	cpu: Useful getters for ActivityRecorder	Andrew Bardsley
2014-05-09	cpu: Add flag name printing to StaticInst	Andrew Bardsley
2014-05-09	cpu: Timebuf const accessors	Andrew Bardsley
2014-05-09	arm: Add branch flags onto macroops	Andrew Bardsley
2014-05-09	cpu: Allow setWhen on trace objects	Andrew Bardsley
2014-05-09	arm: add preliminary ISA splits for ARM arch	Curtis Dunham
2014-05-09	arch: teach ISA parser how to split code across files	Curtis Dunham
2014-05-09	config: Avoid generating a reference to myself for Parent.any	Geoffrey Blake
2014-05-09	arch, arm: Preserve TLB bootUncacheability when switching CPUs	Geoffrey Blake
2014-05-09	cpu: add more instruction mix statistics	Curtis Dunham
2014-05-09	mem: Squash prefetch requests from downstream caches	Mitch Hayenga
2014-05-09	stats: Method stats source	Stephan Diestelhorst
2014-05-09	cpu, arm: Allow the specification of a socket field	Akash Bagdia
2014-05-09	mem: Auto-generate CommMonitor trace file names	Sascha Bischoff
2014-05-09	arm: Panics in miscreg read functions can be tripped by O3 model	Geoffrey Blake
2014-05-09	dev: Set HDLCD default pixel clock for 1080p @ 60Hz	Chris Emmons
2014-05-09	arm: quick hack to allow a greater number of CPUs to a guest OS	Matt Evans
2014-05-09	arch: remove inline specifiers on all inst constrs, all ISAs	Curtis Dunham
2014-05-09	arm: cleanup ARM ISA definition	Curtis Dunham
2014-05-09	scons: Require SWIG >= 2.0.4 and remove vector typemaps	Curtis Dunham