gem5 - gem5

Age	Commit message (Expand)	Author
2019-04-05	cpu: Correctly account for executed instructions in simple cpus	Nikos Nikoleris
2019-04-05	mem-cache: ambiguous use of abs function	Ryan Gambord
2019-04-05	mem: Reverse order of write/read mem queue check	Jason Lowe-Power
2019-04-04	mem-cache: AMPM Prefetcher fails when restoring from a checkpoint	Javier Bueno
2019-04-03	misc: Removed inconsistency in O3* debug msgs	Andrea Mondelli
2019-04-03	arch-mips: added missing override specifier (o3)	Andrea Mondelli
2019-04-03	mem-cache: Fix PIF prefetcher compilation error with NULL ISA	Javier Bueno
2019-04-03	mem-cache: ISB prefetcher was triggering an assertion	Javier Bueno
2019-04-03	mem-cache: Fix panic in Indirect Memory prefetcher	Javier Bueno
2019-04-02	dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt	Giacomo Travaglini
2019-04-02	mem-cache: Proactive Instruction Fetch Implementation	Ivan Pizarro
2019-04-01	dev-arm: Correct cast of template parameter	Andrea Mondelli
2019-03-29	systemc: Templatize the gem5/TLM bridge SimObjects.	Gabe Black
2019-03-29	systemc: Delete extra code from src/systemc/tlm_bridge.	Gabe Black
2019-03-29	systemc: Create unified gem5/TLM bridge SimObjects.	Gabe Black
2019-03-29	tlm: Initial import of tlm/gem5 bridge code.	Gabe Black
2019-03-29	systemc: Provide a utility Port TLM socket wrapper class.	Gabe Black
2019-03-28	cpu: Added a probe to notify the address of retired instructions	Javier Bueno
2019-03-28	mem-cache: Remove extra cache header from AMAP	Daniel R. Carvalho
2019-03-28	arch-arm: Fix use of bitwise operators on booleans	Javier Setoain
2019-03-28	arch-arm: Fix index generation for VecElem operands	Giacomo Travaglini
2019-03-27	dev-arm: Rename GIC maintenance interrupt from ppint to maint_int	Giacomo Travaglini
2019-03-27	dev-arm: Fix GICv3 overflow for INTID > 256	Giacomo Travaglini
2019-03-27	dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)	Giacomo Travaglini
2019-03-27	cpu: Fixed the indirect branch predictor GHR handling	Pau Cabre
2019-03-26	mem: Deleting this init() method was accidentally dropped during rebase.	Gabe Black
2019-03-26	mem: Clean up the xbars a little.	Gabe Black
2019-03-26	base: Make AddrRangeMap able to return non-const iterators.	Gabe Black
2019-03-26	dev-arm: Set/Unset dma coherent mode from python	Giacomo Travaglini
2019-03-26	base,python: Fix to allow multiple --debug-ignore values.	Isaac Sánchez Barrera
2019-03-25	arch-arm: Add missing fall-through defaults	Javier Setoain
2019-03-25	arch-power: Rename program counter registers	Sandipan Das
2019-03-25	arch-power: Simplify doubleword operand types	Sandipan Das
2019-03-23	misc: missing override specifier	Andrea Mondelli
2019-03-22	sim-se: Fixed initialization array size	Tiago Muck
2019-03-22	base: Fix CircularQueue's operator-= when negative subtraction	Giacomo Travaglini
2019-03-22	base: Fix CircularQueue when diffing iterators	Giacomo Travaglini
2019-03-21	dev-arm: ambiguous use of getPort()	Andrea Mondelli
2019-03-21	cpu-kvm: Added informative error message	Ryan Gambord
2019-03-20	mem-cache: Added the STeMS prefetcher	Javier Bueno
2019-03-19	systemc: Hook up gem5_getPort to the gem5 getPort mechanism.	Gabe Black
2019-03-19	arch, cpu, dev, gpu, mem, sim, python: start using getPort.	Gabe Black
2019-03-19	python: Switch to the new getPort mechanism to connect ports.	Gabe Black
2019-03-19	mem: Move bind() and unbind() into the Port class.	Gabe Black
2019-03-19	sim: Add a getPort function to SimObject.	Gabe Black
2019-03-18	python: Change \|\| to && for MessageBuffers in connectPorts.	Gabe Black
2019-03-18	python: Improve how templated SimObject classes are handled.	Gabe Black
2019-03-18	scons: fix disable_partial logic for fast binary	Hoa Nguyen
2019-03-18	mem-cache: tautological comparison of byteOrder	Andrea Mondelli
2019-03-15	mem: Removed circular include ref	Ryan Gambord