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2019-04-03misc: Removed inconsistency in O3* debug msgsAndrea Mondelli
Added consistency in the DEBUG message form, to allow a better parsing. Fixed sn/tid type parameter. Removed some annoying newlines Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17248 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-03arch-mips: added missing override specifier (o3)Andrea Mondelli
Change-Id: Ic538825a2964fd62def672b933a83067a15bd12a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17648 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-03mem-cache: Fix PIF prefetcher compilation error with NULL ISAJavier Bueno
Referencing BaseCPU is causing a compilation error when using the NULL ISA. This patch changes the reference to a SimObject, which fixes the problem. Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17731 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-03mem-cache: ISB prefetcher was triggering an assertionJavier Bueno
An assertion ignored the case when an entry of the SP table had been invalidated. Change-Id: I5bf04e7a0979300b0f41f680c371f6397d4cbf3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17734 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-03mem-cache: Fix panic in Indirect Memory prefetcherJavier Bueno
Memory requests with a size non-power-of-two and less than 8 values were causing a panic, but there these should be allowed and ignored by the prefetcher. Change-Id: I86baa60058cc8a7f232d6ba5748d4c24a463c840 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17733 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-02dev-arm: Make GICv3 maintenance interrupt an ArmInterruptGiacomo Travaglini
Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-02mem-cache: Proactive Instruction Fetch ImplementationIvan Pizarro
Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December). Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 152-162). ACM. Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16968 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-01dev-arm: Correct cast of template parameterAndrea Mondelli
Clang with -Wconstant-conversion is _very_ restrictive on casting. The shift operator results in an incorrect promotion. This patch add a compile-time static cast that remove the error when clang is used. Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17308 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-29systemc: Templatize the gem5/TLM bridge SimObjects.Gabe Black
The C++ side is templated, and there are python versions for each (currently two) width of bridge supported. Change-Id: I4baa9f22d4c87629d45e9e1292eb66c65d25a655 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17234 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-29systemc: Delete extra code from src/systemc/tlm_bridge.Gabe Black
Much of the code in src/systemc/tlm_bridge has been absorbed into the TLM/gem5 bridge SimObjects and is no longer needed and redundant with the original version in util/. Change-Id: I0fa7af67649987cf9f6fc5cd4783002dde2242ac Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17233 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-29systemc: Create unified gem5/TLM bridge SimObjects.Gabe Black
These objects expose a standard TLM initiator or target socket with width 64, and a gem5 slave or master port. What goes in one type of port comes out the other with the appropriate conversion applied. Change-Id: I65e07f746d46d3db0197968b78fffc5ddaede9bf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17232 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-29tlm: Initial import of tlm/gem5 bridge code.Gabe Black
This is a slightly mangled version of the existing bridge code in util/tlm/src/. The changes fix some small style issues, change to gem5 specific include paths, and removes the Gem5SimControl code. That code coordinates gem5 with the external systemc kernel, and in this usage there's no external kernel. The code imported here compiles, but it isn't yet expected to work. Change-Id: I9c593a52e2554534720d21cd31a03e543ad897ad Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17231 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-29systemc: Provide a utility Port TLM socket wrapper class.Gabe Black
This class should make it easy to attach TLM sockets into the gem5 python Port config mechanism. Change-Id: I3548c654d56bfc852f3fc98fe6433163b14f7fe3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17230 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-28cpu: Added a probe to notify the address of retired instructionsJavier Bueno
A probe is added to notify the address of each retired instruction. Change-Id: Iefc1b09d74b3aa0aa5773b17ba637bf51f5a59c9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17632 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-28mem-cache: Remove extra cache header from AMAPDaniel R. Carvalho
The cache header was being included in the AMAP, although not used, which resulted in slightly longer compilation time. Change-Id: I3654bc719c6b5f558af116addae159301602a3cf Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17711 Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-28arch-arm: Fix use of bitwise operators on booleansJavier Setoain
Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17288 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-28arch-arm: Fix index generation for VecElem operandsGiacomo Travaglini
Current operand generation is not providing VecElems with the right vector index and element index. The bug was covered when registers were 128 bit wide, but with SVE we have augmented the vector register size and the bug has been exposed. E.g. With dest = 2, FpDestP2 = (vec_index = 0, elem_index = 4) whereas it should be FpDestP2 = (vec_index = 1, elem_index = 0) Change-Id: Iad02fb477afd0d3dd3d437bf2ca4338fbd142107 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17710
2019-03-27dev-arm: Rename GIC maintenance interrupt from ppint to maint_intGiacomo Travaglini
ppint is a generic name which only reflects Arm recommendation of assigning the maintanance interrupt to a PPI (numbered 25) Change-Id: Ic5abb6ed50817ad2d165b5df46dd989eb195a9db Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17628 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27dev-arm: Fix GICv3 overflow for INTID > 256Giacomo Travaglini
SPIs can get to a maximum number of 1023, so that an uint8_t is not capable of representing all of them. Change-Id: I7a2c43b41ac93eabdfcf8311681240416b954177 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17631 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)Giacomo Travaglini
For SGIs and PPIs: * When ARE is 1 (only value supported in gem5) for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case. Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27cpu: Fixed the indirect branch predictor GHR handlingPau Cabre
The internal indirect predictor global history was not being updated properly, resulting in higher than expected miss rates Also added a parameter to set the size of the indirect predictor GHR Change-Id: Ibc797816974cba6719da65122801e8919559a003 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reported-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16928 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-26mem: Deleting this init() method was accidentally dropped during rebase.Gabe Black
Deleting this init() method was part of a change just committed, but was accidentally dropped during a rebase. Change-Id: I0f22778596ed11e182f3111d9999a0fef727f6cc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17688 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-26mem: Clean up the xbars a little.Gabe Black
Get rid of comments which just restate the code, get rid of redundant "virtual" keywords, add "override"s, fix style, and get rid of xbar::init which was empty and hiding the parent class init. Change-Id: I8ce20abee340baa88084d142f2fb8c633ee54ba9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17592 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-26base: Make AddrRangeMap able to return non-const iterators.Gabe Black
The erase() method only accepts regular iterators which is consistent with the normal STL map, but the existing find() only returns const iterators. The STL container can return either depending on if "this" is const. Unfortunately there isn't a great way to have only one find implementation which returns the right type of iterator under the right conditions. Also, it's not possible to turn a const_iterator into an iterator, but it is possible to go the other way. This change duplicates very short functions which return iterators, and for find does the only thing I could find which avoids having to copy that whole large function. Change-Id: I2f789b5d0881feb9adff9978bd40e31731c6a688 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17588 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-26dev-arm: Set/Unset dma coherent mode from pythonGiacomo Travaglini
With this patch it will be possible to automatically enable/disable the dma-coherent property for the GenericArmPciHost autogenerated DTB. This has been done by adding the _dma_coherent param. Change-Id: I1759fced74e42410462637ca77997a351314a90a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16748 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-26base,python: Fix to allow multiple --debug-ignore values.Isaac Sánchez Barrera
When adding multiple SimObjects to --debug-ignore, either separating the values with a colon or adding multiple --debug-ignore flags, the previous code only ignored the last SimObject in the list. This changeset adds and uses new `ObjectMatch::add` and `Logger::addIgnore` methods to make the functionality of the flag consistent with its description. Change-Id: Ib6967a48611ea59a211f81af2a970c4de429b1be Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17488 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-25arch-arm: Add missing fall-through defaultsJavier Setoain
Change-Id: Ie64b83d754c4719a77c7788879be71304a9b786e Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17289 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-25arch-power: Rename program counter registersSandipan Das
The Power ISA specification lists the Program Counter (PC) and the Next Program Counter (NPC) registers as Current Instruction Address (CIA) and Next Instruction Address (NIA). This applies the ISA naming convention for these two registers. Change-Id: I8b9094ab1c809f4dfdb4d7330c17f360adf063e9 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16603 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-25arch-power: Simplify doubleword operand typesSandipan Das
Currently, 'sq' and 'uq' are used to represent signed and unsigned doublewords respectively. Since all recent Power ISA specifications list 128-bit quadwords as a valid data type, it may be misleading to use the current terminology in case support for such operands are added in the future. So, to simplify this, 'sd' and 'ud' are used to represent signed and unsigned doublewords respectively. Change-Id: Ie7831c596fc8f9ddfdf3b652c37cfe26484ebe01 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16602 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-23misc: missing override specifierAndrea Mondelli
Missing specifier of overridden virtual function declared in sim_object.hh Removed redundant "virtual" keyword Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-22sim-se: Fixed initialization array sizeTiago Muck
Doubled the size of the zeroed auxiliary vector since 2 * intSize on aarch64 > sizeof(uint64). Change-Id: I5196b000a696e9ea3f2b5daa5d5bb071794369aa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17088 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-03-22base: Fix CircularQueue's operator-= when negative subtractionGiacomo Travaglini
Using operator-= when the rhs is a negative value is equivalent to using += on -rhs. This is fixing rounding in that scenario. Change-Id: Ia22e51f81a6805d27fd6b2115d288bb23421d00f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17528 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-22base: Fix CircularQueue when diffing iteratorsGiacomo Travaglini
This patch is fixing CircularQueue iterators' subtraction, in particular the behaviour when head and tail round multiple times. Change-Id: Ie79ac8accd30a10cf039cf4def87675b01375d6b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17188 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-21dev-arm: ambiguous use of getPort()Andrea Mondelli
The recent introduction of getPort() creates a conflict with the existing method used in arm MMU. This patch rename the old getPort() in getDMAPort() according to the returned value (DmaPort class type) Change-Id: Ief3d83650fd6b08490522341631244be06e380ce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17469 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-21cpu-kvm: Added informative error messageRyan Gambord
PerfKvmCounter::attach fails if the user doesn't have privileges to make the perf_event_open syscall. This is the default privilege setting since kernel 4.6. I've seen some users in the mailing list resort to running as root; changing the perf_event_paranoid setting is an alternative. Change-Id: I2bc6f76abb6e97bf34b408a611f64b1910f50a43 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17508 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-20mem-cache: Added the STeMS prefetcherJavier Bueno
Reference: Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and Babak Falsafi. 2009. Spatio-temporal memory streaming. In Proceedings of the 36th annual international symposium on Computer architecture (ISCA '09). ACM, New York, NY, USA, 69-80. Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16423 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-19systemc: Hook up gem5_getPort to the gem5 getPort mechanism.Gabe Black
Change-Id: I771607c4436f4c1ca9d355d1da52924308cfc3b3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17229 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19python: Switch to the new getPort mechanism to connect ports.Gabe Black
This retrieves ports using the getPort method, and connects them using the bind method on the ports themselves. Any smarts as far as what type of peers are allowed to connect or how they connect is left up to the individual bind methods. Change-Id: Ic640d1fce8af1bed411116e5830edc4a8a0f9d66 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17039 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19mem: Move bind() and unbind() into the Port class.Gabe Black
These are now pure virtual methods which more specialized port subclasses will need to implement. The SlavePort class implements them by ignoring them and then providing parallel functions for the MasterPort to call. The MasterPort's methods do basically what they did before, except now bind() uses dynamic cast to check if its peer is of the appropriate type and also to convert it into that type before connecting to it. Change-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17038 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19sim: Add a getPort function to SimObject.Gabe Black
This will retrieve a Port object from a given SimObject (which might not be a MemObject) no matter what flavor of Port it is. Change-Id: I636b85e9d4929a05a769e165849106bcb5f3e9c1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17037 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-18python: Change || to && for MessageBuffers in connectPorts.Gabe Black
The connectPorts function currently checks if *either* of the peers in a port connection are a MessageBuffer, and if so will ignore the connection. This CL changes that || into a && so that *both* of the peers need to be a Ruby types (either a MessageBuffer or Network) for the connection to be ignored. That makes it easier to contain that abnormal behavior to those types instead of having it apply even when other types of port owners are involved. Unfortunately the number of interesting Ruby types is unbounded, but these are the types with ports as of today. This mechanism will hopefully be replacedall together so this should be a temporary issue. Change-Id: I140498770e5d37eb2abd3d99261d47e111f1c8ab Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17031 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-03-18python: Improve how templated SimObject classes are handled.Gabe Black
When setting up a SimObject's Param structure, gem5 will autogenerate a header file which attempts to declare the SimObject's C++ type. It has had at least some level of sophistication there where it would pull off the namespaces ahead of the class name and handle them properly, but it didn't know how to handle templates. This change improves that handling in two ways. First, it adds a new magical SimObject attribute called 'cxx_template_params' which is used to specify what the template parameters are as a list. For instance, if your SimObject was a template which took an integer constant as its first parameter and a type as its second, this attribute could look like the following: cxx_template_params = [ 'int FOO', 'class Bar' ] Importantly, if there are any default values for these template parameters, they should *not* be included here, they should be specified where the class is later defined. The second new mechanism is to add an internal CxxClass in the SimObject.cxx_param_decl method. This class accepts the class signature in the cxx_class attribute and the cxx_template_params and does two things. First, it strips off namespaces like in the old implementation. Second, it extracts and processes any template arguments attached to the class. If these are constants (as determined by the contents of cxx_template_params), then they are stored verbatim. If they're types, then they're recursively expanded into a CxxClass and stored that way. Note that these are the *values* of the template arguments, where as cxx_template_params lists the *types* and *names* of those arguments. In our earlier example, if cxx_class was: cxx_class = 'CoolClasses::ClassName<12, Fruit::Apple>' Then CxxClass would extract the namespace 'CoolClasses', the class name 'ClassName', the argument '12', and the argument 'Fruit::Apple'. That second argument would be expanded into a CxxClass with the namespace 'Fruit' and the class name 'Apple'. Importantly here, because there were no default arguments given in cxx_template_params, all "hidden" arguments which would fall through to their defaults need to be fully specified in cxx_class. The CxxClass has a method called declare() which uses the information extracted earlier to output all of the "stuff" necessary for declaring the given class, including opening any containing namespaces and putting template<...> ahead of the actual class declaration with the template parameters specified. If any of the template arguments are themselves CxxClass instances, then they'll be recursively declared immediately before the current class is. An alternative solution to this problem might be to include the header file which actually defines the cxx_class type to avoid having to come up with a declaration. Unfortunately this doesn't work since it can set up include loops where the SimObject C++ header file includes the param header to get access to the Param type, but that includes the C++ header to get access to the SimObject type. This also makes it harder for SimObjects to refer to each other, since they rely on the declaration in the params header files when declaring a member pointer to that type in their own Param structures. Change-Id: I68cfc36ddff6d789eb4cdef5178c4619ac2cc8b1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17228 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-18scons: fix disable_partial logic for fast binaryHoa Nguyen
Partial linking should be disabled on darwin; however, the script fails to do so when force_lto is set, which results in gem5 building with fast option fails on macOS. This fix changes disable_partial logic, which should be True once it's True. Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Change-Id: I77d2a4cc4a9bf5c92c800c004eb744bb7081c42e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16888 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-03-18mem-cache: tautological comparison of byteOrderAndrea Mondelli
Error: build/X86/mem/cache/prefetch/indirect_memory.cc:56:24: error: result of comparison of constant -1 with expression of type 'const ByteOrder' is always false [-Werror,-Wtautological-constant-out-of-range-compare] fatal_if(byteOrder == -1, "This prefetcher requires a defined ISA\n"); ~~~~~~~~~ ^ ~~ build/X86/base/logging.hh:205:14: note: expanded from macro 'fatal_if' if ((cond)) { \ ^~~~ 1 error generated. Fix: cast of constant (-1) used in comparison Change-Id: I3deb154c2fe5b92c4ddf499176cb185c4ec7cf64 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17388 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-15mem: Removed circular include refRyan Gambord
If BasicLink.hh is modified, the style checker forces a reordering of the includes, which results in build errors because it ends up including Topology.hh before including its xxxParams.hh files, which include forward declarations of the BasicLink family of classes, and so Topology.hh throws errors that BasicLink etc. are not declared. Change-Id: I664a0652e53f0cc61763c2190a980c655b85d397 Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17270 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-15mem-cache: Added the Indirect Memory PrefetcherJavier Bueno
Reference: Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas. 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807 Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16223 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-15mem: Move the Port base class into sim.Gabe Black
The Port class is going to be officially used for more than just memory system connections. Change-Id: I493e721f99051865c5f0c06946a2303ff723c2af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17036 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-15dev: Make EtherInt inherit from Port.Gabe Black
This way a common function can return EtherInt (and master and slave ports). Change-Id: I1215baaad918ef0352b228877241b2b6dd2503fc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17035 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-15mem: Track the MemObject owner in MasterPort and SlavePort.Gabe Black
These types are much more tied to MemObjects and the gem5 memory protocol than the Port or BaseMasterPort and BaseSlavePort classes. Change-Id: I36bc8c75b9c74d28ee8b65dbcbf742cd41135742 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17032 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-09 13:51:51 +0000