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2018-03-27arch: cpu: Make the ExtMachInst type a template argument in InstMap.Gabe Black
This doesn't completely hide the ISA specific ExtMachInst type inside the ISAs since it still gets applied in arch/generic, but it at least pulls it into the arch directory. Change-Id: Ic2188d59696530d7ecafdff0785d71867182701d Reviewed-on: https://gem5-review.googlesource.com/9403 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-27sparc: Add some missing M5_FALLTHROUGHs and breaks.Gabe Black
These fix what I believe are some bugs, and also some gcc warnings. Change-Id: I5fb2a1b2f0ef3643b25aaf0c29c096996ef98ec0 Reviewed-on: https://gem5-review.googlesource.com/9402 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-27cpu: Stop extracting inst_flags from the machInst.Gabe Black
The instruction representation is already encoded in the trace protobuf, so there's no reason to encode a part of it again. This is especially true since this supposedly generic code is extracting the first 8 bits of the machInst, a totally arbitrary set of bits for most ISAs. If certain bits within a machine instruction are actually relevant, the consumer of the trace should be able to interpret the instruction bytes which are already there and extract the same bits within the context of whatever ISA they're appropriate for. Change-Id: Idaebe6a110d7d4812c3d7c434582d5a9470bcec1 Reviewed-on: https://gem5-review.googlesource.com/9401 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-26cpu: Proposed fix for backwards compatibility in proto/inst.proto.Gabe Black
I haven't tested this at all, but this may fix backwards compatibility in inst.proto by removing the oneof construct. Change-Id: Iba19744791c2c577c3b442402f8cc6dcef8550bd Reviewed-on: https://gem5-review.googlesource.com/9361 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-26arch: Fix all override related warnings.Gabe Black
Clang has started(?) reporting override related warnings, something gcc apparently did before, but was disabled in the SConstruct. Rather than disable the warnings in for clang as well, this change fixes the warnings. A future change will re-enable the warnings for gcc. Change-Id: I3cc79e45749b2ae0f9bebb1acadc56a3d3a942da Reviewed-on: https://gem5-review.googlesource.com/9343 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-26cpu: Use the new asBytes function in the protobuf inst tracer.Gabe Black
Use this function to get the binary representation of the instruction rather than referencing the ExtMachInst typed machInst member of the StaticInst directly. ExtMachInst is an ISA specific type and can't always be straightforwardly squished into a 32 bit integer. Change-Id: Ic1f74d6d86eb779016677ae45c022939ce3e2b9f Reviewed-on: https://gem5-review.googlesource.com/7563 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-26arch: Add a virtual asBytes function to the StaticInst class.Gabe Black
This function takes a pointer to a buffer and the current size of the buffer as a pass by reference argument. If the size of the buffer is sufficient, the function stores a binary representation of itself (generally the ISA defined instruction encoding) in the buffer, and sets the size argument to how much space it used. This could be used by ISAs which have two instruction sizes (ARM and thumb, for example). If the buffer size isn't sufficient, then the size parameter should be set to what size is required, and then the function should return without modifying the buffer. The buffer itself should be aligned to the same standard as memory returned by new, specifically "The pointer returned shall be suitably aligned so that it can be converted to a pointer of any complete object type and then used to access the object or array in the storage allocated...". This will avoid having to memcpy buffers to avoid unaligned accesses. To standardize the representation of the data, it should be stored in the buffer as little endian. Since most hosts (including ARM and x86 hosts) will be little endian, this will almost always be a no-op. Change-Id: I2f31aa0b4f9c0126b44f47a881c2901243279bd6 Reviewed-on: https://gem5-review.googlesource.com/7562 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-23mem-cache: fix missing overrides in repl policiesJason Lowe-Power
Change-Id: I67759a4532e8a46c1643d4c3a9c546ad6b565b81 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/9321 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23ruby: Make sure addresses print in hexJason Lowe-Power
Added fix in the invalid transition panic and various places in ruby random tester. Change-Id: I879264da58369faf7de49d1a28b2da1cb935ef0a Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8941 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23learning_gem5: Add a simple Ruby protocolJason Lowe-Power
Adds the MSI protocol from "A Primer on Memory Consistency and Cache Coherence" by Daniel J. Sorin, Mark D. Hill, and David A. Wood. This code follows Learning gem5 Part 3. http://learning.gem5.org/book/part3/index.html This is meant to be a simple, clean, example of how to make a Ruby protocol. Currently, it only works in SE mode. The next changeset will contain the required configuration files. Change-Id: If2cc53f5e6b9c6891749f929d872671615a2b4ab Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8942
2018-03-23mem-cache: Create FIFO replacement policyDaniel R. Carvalho
Implementation of a First-In, First-Out replacement policy. Change-Id: Id234ec9d29c092dd4516e609da14b8a75a96b5e4 Reviewed-on: https://gem5-review.googlesource.com/8888 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23mem-cache: Fix MRU rebaseDaniel R. Carvalho
Rebase of MRU missed a const qualifier, introducing a compilation error. Change-Id: Ia25aa30523613a1a87593a353abe439946656f63 Reviewed-on: https://gem5-review.googlesource.com/9301 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23arch-arm: Distinguish IS TLBI from non-ISGiacomo Travaglini
TLBI broadcasting was the default implementation of most of TLBI instructions. This patch applies the broadcasting behaviour only to the Inner-Shareable subset, while simpler TLB invalidation instructions only affect the PE that executes them. Change-Id: Idb01d0d4f593131f657e8fc9668112de8e4ccdcb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9182 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-23arch-arm: Created function for TLB ASID InvalidationGiacomo Travaglini
This patch is intended to avoid code duplication and extends the set of TLBI ISA functions adding the entry invalidation by ASID match. Change-Id: I9bcb498059ea480dd2118639c7b3c64fea80a5e1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9181 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-22hsail: Get rid of an inert private member of StorageSpace.Gabe Black
The "segment" private element in this class was only ever set to zero on construction, and then used to index into a list of segment names to get the string "none" in a DPRINTF. If debugging was turned off, there would be no consumers of that variable, and that upset g++. This change removes the essentially useless variable, and also that bit of text in the DPRINTF. Change-Id: I3f85db4af5f0678768243daf84b8d698350af931 Reviewed-on: https://gem5-review.googlesource.com/9221 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-03-22cpu: Make the protobuf inst tracer accept variable sized instructions.Gabe Black
This change adds an inst_bytes field which is of type bytes, and puts it in a oneof with the previously required inst field. If an instruction's encoding happens to be 4 bytes long, the original inst field will be used. Otherwise, the new variably sized inst_bytes field will be used. Because this tracer doesn't have visibility into how the data in inst_bytes is structured, it can't do any endian conversion itself. To maintain compatibility between producers and consumers who may have different endiannesses, all data should be manually converted to little endian before being stored in this field. inst will be converted into little endian by protobuf, and so compatibility doesn't have to be handled manually. Change-Id: I290713f70e7124d8aa9550c022c71334939d84a6 Reviewed-on: https://gem5-review.googlesource.com/7561 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-22mem-cache: Create MRU replacement policyDaniel R. Carvalho
Implementation of a Most Recently Used replacement policy. Change-Id: Id52cb247ca25d4523dcc53490d113695dac6a3f1 Reviewed-on: https://gem5-review.googlesource.com/8889 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-22mem-cache: Split array indexing and replacement policies.Daniel R. Carvalho
Replacement policies (LRU, Random) are currently considered as array indexing methods, but have completely different functionalities: - Array indexers determine the possible locations for block allocation. This information is used to generate replacement candidates when conflicts happen. - Replacement policies determine which of the replacement candidates should be evicted to make room for new allocations. For this reason, they were split into different classes. Advantages: - Easier and more straightforward to implement other replacement policies (RRIP, LFU, ARC, ...) - Allow easier future implementation of cache organization schemes As now we can't assure the use of sets, the previous way to create a true LRU is not viable. Now a timestamp_bits parameter controls how many bits are dedicated for the timestamp, and a true LRU can be achieved through an infinite number of bits (although a few bits suffice in practice). Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda Reviewed-on: https://gem5-review.googlesource.com/8501 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-21mem-cache: Allow clean operations when block allocation failsNikos Nikoleris
Block allocation can fail when there is an in-service MSHR that operates on the victim block. This can happed due to: * an upgrade operation: a request that needs a writable copy of the block finds a shared (non-writable) copy of the block in the cache and has allocates an MSHR for the pending upgrade operation, or * a clean operation: a clean request finds a dirty copy of the block and allocates an MSHR for the pending clean operation. This changes relaxes an assertion to allow for the 2nd case (cache clean operations). Change-Id: Ib51482160b5f2b3702ed744b0eac2029d34bc9d4 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9021 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-20arch-arm, configs: Treat the bootloader rom as cacheable memoryNikos Nikoleris
Prior to this changeset the bootloader rom (instantiated as a SimpleMemory) in ruby Arm systems was treated as an IO device and it was fronted by a DMA controller. This changeset moves the bootloader rom and adds it to the system as another memory with a dedicated directory controller. Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8741 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-03-20arch, arm: Fix implicit-fallthrough GCC warningsChun-Chen Hsu
GCC 7 generates spurious fallthrough warnings in nested switch blocks where the inner switch block return. There is already a GCC fix [1] submitted for review but, until it is merged into GCC trunk, GEM5 will not build with GCC 7 due to these fallthrough warnings. This patch silences the spurious fallthrough warnings by appending a M5_UNREACHABLE statement in the outer switch cases. Note there is another GEM5 patch [2] to fix other fallthrough warnings. [1] https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01105.html [2] https://gem5-review.googlesource.com/c/public/gem5/+/8541 Change-Id: I97cd8bfa90a88e93cee60cf27a8c93611d11a242 Signed-off-by: Chun-Chen Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/9101 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-03-20riscv: throw IllegalInstFault when decoding invalid instructionsTuan Ta
If an instruction is invalid, some assertions may in the decoder may fail the entire simulation. Instead, we want to raise an IllegalInstFault instead of failing immediately in the decoder if the invalid instruction is being speculatively executed. Change-Id: I5cb72ba06f07f173922f86897ddfdf677e8c702f Reviewed-on: https://gem5-review.googlesource.com/9261 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Monir Zaman <monir.zaman.m@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-03-15arm: Fix implicit-fallthrough warnings when building with gcc-7+Siddhesh Poyarekar
gcc 7 onwards have additional heuristics to detect implicit fallthroughs and it fails the build with warnings for ARM as a result. There was one gcc bug[1] that I fixed but the rest are cases that gcc cannot detect due to the point at which it does the fallthrough check. Most of this patch adds __builtin_unreachable() hints in places that throw this warning to indicate to gcc that the fallthrough will never happen. The remaining cases are actually possible fallthroughs due to incorrect code running on the simulator; in which case an Unknown instruction is returned. [1] https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01105.html Change-Id: I1baa9fa0ed15181c10c755c0bd777f88b607c158 Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/8541 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-03-15arch-x86,sim-se: Enable prlimit syscallJason Lowe-Power
Change-Id: I15f0e5ddb72578de90ed68866c8a0c1501717d61 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8921 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-03-15sim-se: Fix fallthrough in prlimitJason Lowe-Power
Change-Id: Ieec4651000b3b4de05ba5ba11fdfa5392a5477e7 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8904 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-03-15arch-x86,sim-se: Bump kernel version to 3.2Jason Lowe-Power
Current glibc expects at least kernel 3.2. Bump this so syscall emulation with dynamically-linked binaries works. Change-Id: I07077ed2de14c308f6ff79cae677915612557332 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8903 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-03-15sim-se: Add /sys/devices/system/cpu/online fileJason Lowe-Power
Add the special file /sys/devices/system/cpu/online to the files that gem5 knows how to handle in SE mode. This file lists the CPUs that are active. For instance, in an 8 CPU system it is the following: 0-7 This implementation simply returns a file that is 0-%d where %d is the current number of thread contexts. This file is required for C++11 threads with gcc 4.8 and above. Change-Id: I0b566f77e75e9eca480509814d0fd038a231b940 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8902 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-03-15arch-arm: Fix unused variable warning in faults.ccNikos Nikoleris
Change-Id: Ife4a2189e140cdefcf53fa88213d8a5225067457 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9201 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-03-15x86: Add bitfields which can gather/scatter bases and limits.Gabe Black
Add bitfields which can gather/scatter base and limit fields within "normal" segment descriptors, and in TSS descriptors which have the same bitfields in the same positions for those two values. This centralizes the code which manages those bitfields and makes it less likely that a local implementation will be buggy. Change-Id: I9809aa626fc31388595c3d3b225c25a0ec6a1275 Reviewed-on: https://gem5-review.googlesource.com/7661 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14x86: Simplify the implementations of RDTSC and RDTSCP slightly.Gabe Black
These instructions originally read the TSC into t1 and then unpacked it into eax and edx using a move, a right shift, and then another move. We can combine the second shift and move. The shift will move the upper 32 bits into the lower 32 bits, and clear the upper 32 bits to zero. This has the same effect as moving the lower 32 bits post-shift into another register, since the upper 32 bits will be cleared to zero based on x86 partial register access semantics. Change-Id: Iba85e501c7e84147ad0047f5c555e61bdf8f032b Reviewed-on: https://gem5-review.googlesource.com/9044 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14x86: Implement the RDTSCP instruction.Gabe Black
This is very similar to RDTSC, except that it requires all younger instructions to retire before it completes, and it writes the TSC_AUX MSR into ECX. I've added an mfence as an iniitial microop to ensure that memory accesses complete before RDTSCP runs, and added an rdval microop at the end to read the TSC_AUX value into ECX. Change-Id: I9766af562b7fd0c22e331b56e06e8818a9e268c9 Reviewed-on: https://gem5-review.googlesource.com/9043 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14x86: Mark the RDTSC instruction as .serialize_before.Gabe Black
Change-Id: I20bf6a57ea4354aac9267845bb37b70b83d6fcde Reviewed-on: https://gem5-review.googlesource.com/9042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14x86: Replace the .serializing directive with .serialize_(before|after).Gabe Black
This makes it explicit which type of serialization you want, and also makes it possible to make a macroop serialize before. The old serializing directive was renamed .serialize_after in the microcode assembler, and throughout the microcode implementation, and its behavior is unchanged. More specifically, it still marks the last microop within the macroop as IsSerializing and IsSerializeAfter. The new .serialize_before directive does something similar and marks the first microop as IsSerializing and IsSerializeBefore. Change-Id: Ia53466c734c651c65400809de7ef903c4a6c3e7e Reviewed-on: https://gem5-review.googlesource.com/9041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14arm: Fix maybe-uninitialized GCC warningsChun-Chen Hsu
GCC 7 generates maybe-uninitialized warnings at the code that updates the "dest" variables in the writeVecElem function of neon64_mem.hh file. It is because the generated code does not appropriately initialize the output variable before passing it to the writeVecElem function. This patch initializes the output variable to fix this. Change-Id: I50a8f4e456ccdcaa3db1392ec097017450c56ecb Signed-off-by: Chun-Chen Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/9121 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-14base: Fix loop range in pngwriterChun-Chen Hsu
The inner loop range limit should be width instead of height. Change-Id: I091c590713c945d4bd04ffcc974d4eb8aa23d1b2 Signed-off-by: Chun-Chen Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/9081 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-03-14arch-arm: ERET from AArch64 to AArch32 ignore MSBsGiacomo Travaglini
The 32 most significant bits of ELR_ELx must be ignored when returning from AArch64 to AArch32. Change-Id: I412d72908997916404e16e9eeca2789a9c529e58 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8881 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-12mem-ruby: Fix RubyPrefetcher support in MESI_Two_LevelRico Amslinger
Only a small quantity of prefetches were issued, as the positive feedback mechanism was not implemented. This commit adds a new action po_observeHit, which notifies the RubyPrefetcher of successful prefetches and resets the prefetch flag. When a cache line was replaced by a prefetch, the wrong queue could be stalled. This commit adds a new event PF_L1_Replacement, which stalls the correct queue. The behavior when receiving a prefetch or instruction fetch while in PF_IS_I (prefetch caused GETs, but got invalidated before the response was received) was undefined. This was changed to drop the prefetch request or change the state to non-prefetch, respectively. This behavior is analogous to IS_I (non-prefetch caused GETs, but got invalidated before the response was received) and the data case, respectively. In my local branch a major (20+%) performance increase can be observed in SPEC2006 gobmk and leslie3d when enabling the prefetcher. Some other benchmarks like bwaves, GemsFDTD, sphinx and wrf show smaller (~10%) performance increases. Unfortunately, the performance in most other SPEC benchmarks is still poor, most likely as the prefetcher does not detect strides fast/often enough. In order to push the change timely (most benchmarks have runtimes in the order of days on my machine even with the smallest parameters) after checkout, I have only run gobmk with the base repository + this commit. The results match those of my local branch. Change-Id: I9903a2fcd02060ea5e619b409f31f7d6fac47ae8 Reviewed-on: https://gem5-review.googlesource.com/8801 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Swapnil Haria <swapnilster@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-03-12arch-arm: Adding IPA-Based Invalidating instructionsGiacomo Travaglini
This patch introduces the TLB IPA-Based invalidating instructions in aarch32. In the entry selection policy the level of translation is not taken into account. This means that no difference stands between (e.g.) TLBIIPAS2 and TLBIPAS2L. Change-Id: Ieeb54665480874d2041056f356d86448c45043cb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8822 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-12arch-arm: Implement missing aarch32 TLBI registersGiacomo Travaglini
In the pool of TLB Invalidate system register a category of instruction was missing: the ones operating on entries added to the TLB during the last level only of a table walk. (E.g. TLBIVMAL). This patch is not considering this matching criteria when invalidating the entries and it is rather performing the invalidation on all levels. Change-Id: I5f2186cfdd73793e76c90b260f7128be187903fe Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8821 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-09mem-cache: Use CacheBlk parameter on address regenerationDaniel R. Carvalho
Skewed caches need to know the way to regenerate a block address. Change-Id: I62c61ac9509eff2f37bad36862751956db7a6e40 Reviewed-on: https://gem5-review.googlesource.com/8782 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-08mem-cache: Fix missing overridesJason Lowe-Power
clang doesn't like inconsistent overrides. Add override to all overidden functions in lru.hh Change-Id: I100ff4a7d90757439afee879ff9838c15f5c0b1d Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8861 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-08sparc: Passify a new g++ warning.Gabe Black
g++ seems to think there are some missing brackets when initializing the sparc fault information. Passify it by adding extra brackets. Change-Id: I826995f88b8ac8a21721c949a244dec480831b80 Reviewed-on: https://gem5-review.googlesource.com/8763 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2018-03-08arch-arm: Enable Debug IFSC when faulting to aarch64 modeGiacomo Travaglini
Previous code was aborting simulation when a debug exception taken in aarch64 mode was encountered. This because an invalid (0xff) instruction fault status code was produced. Change-Id: I289f93f672be70cfbdc404be536809835160bdaf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8363 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-08arch-arm: Fix FSC generation in AbortFaultGiacomo Travaglini
The fault status code generated by a Prefetch/Data Fault was containing a wrong value when the fault was triggered in aarch32 but handled in aarch64. This because the encoding differs between the two ISAs and the encoder was just checking the starting ISA rather than the the ending one. In this case the getFsr must be called after we know which is the ending ISA, which happens only after ArmFault::invoke gets called. The fsc update hence happens before writing into the Syndrome register. Change-Id: I725f12b6dcc0178f608233bd3d15e466d1cd1ffc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8362 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-08arch-arm: Introduce update method in ArmFault classGiacomo Travaglini
There is a set of internal variables in ArmFault thats get updated once the fault is invoked (ArmFault::invoke). Sometimes we rely on those even if the fault is generated but not invoked (e.g. when checking if a memory access is producing a fault). This patch is moving the update functionalities inside a public method so that a client can make use of it even when not invoking the fault. Change-Id: I3ac5b6835023f28ec569fe25487dffa356e1b2fd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8361 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-08arch-arm: Fix PCAlignmentFault routing to HypervisorGiacomo Travaglini
This patch enables PCAlignmentFault routing to Hypervisor in case HCR_EL2.TGE == 1, as is happening for other arm exceptions. Change-Id: I48364ef1a0bcb5d030135221ae4bc6429e32759e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8841 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-07mem-cache: Make the block invalidate functions virtualNikos Nikoleris
This change makes the cache block invalidation function in the BaseTags and CacheBlk class virtual to enable derived classes. Change-Id: I2e64b01c6ca637f16d10474fc8b08eeec3f23453 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8287 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-07mem-cache: Make invalidate a common function between tag classesNikos Nikoleris
invalidate was defined as a separate function in the base associative and fully-associative tags classes although both functions should implement identical functionality. This patch moves the invalidate function in the base tags class. Change-Id: I206ee969b00ab9e05873c6d87531474fcd712907 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8286 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-07mem-cache: Allow prefetchers to override setCache.Xiaoyu Ma
This lets them hook setCache, perhaps to set up additional state based on the set cache. Change-Id: Ic3b34fa43d052c71e8ef733a57fe47c70899cd27 Reviewed-on: https://gem5-review.googlesource.com/8701 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-06scons: Switch from the print statement to the print function.Gabe Black
Starting with version 3, scons imposes using the print function instead of the print statement in code it processes. To get things building again, this change moves all python code within gem5 to use the function version. Another change by another author separately made this same change to the site_tools and site_init.py files. Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0 Reviewed-on: https://gem5-review.googlesource.com/8761 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>