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2015-08-03ruby: mesi two,three level: copy data only when dirtyNilay Vaish
The level 2 controller has a bug. In one particular action, the data block was copied from a message irrespective whether the block is dirty or not. In cases when L1 sends no data, the data value copied was incorrect.
2015-08-01ruby: removed invalid assert in message comparitorBrad Beckmann
It is perfectly valid to compare the same message and the greater than operator should work correctly.
2015-07-20ruby: improved stall and wait debuggingBrad Beckmann
Added dprintfs and asserts for identifying stall and wait bugs.
2015-07-20slicc: fix error in conflicing symbol declarationBrad Beckmann
2015-07-20slicc: enable overloading in functions not in classesBrad Beckmann
For many years the slicc symbol table has supported overloaded functions in external classes. This patch extends that support to functions that are not part of classes (a.k.a. no parent). For example, this support allows slicc to understand that mapAddressToRange is overloaded and the NodeID is an optional parameter.
2015-07-20ruby: change router pipeline stages to 2David Hashe
This patch changes the router pipeline stages from 4 to 2. The canonical 4-stage router is conservative while a lower-latency router with look ahead routing and speculative allocation is well acknowledged.
2015-07-20ruby: change advance_stage for flit_dDavid Hashe
Sets m_stage.second to the second parameter of the function. Then, for every place where advance_stage is called, adds a cycle to the argument being passed.
2015-07-20slicc: improved stalling support in protocolsBrad Beckmann
Adds features to allow protocols to reschedule controllers when conditionally stalling within inport logic or actions. Also insures that resource and protocol stalls are re-evaluated the next cycle.
2015-07-20ruby: expose access permission to replacement policiesDavid Hashe
This patch adds support that allows the replacement policy to identify each cache block's access permission. This information can be useful when making replacement decisions.
2015-07-20ruby: adds size and empty apis to the msg buffer stallmapDavid Hashe
2015-07-20ruby: fix deadlock bug in banked array resource checksDavid Hashe
The Ruby banked array resource checks (initiated from SLICC) did a check and allocate at the same time. If a transition needs more than one resource, then it might check/allocate resource #1, then fail to get resource #2. Another transition might then try to get the same resources, but in reverse order. Deadlock. This patch separates resource checking and resource reservation into two steps to avoid deadlock.
2015-07-20ruby: Fix for stallAndWait bugDavid Hashe
It was previously possible for a stalled message to be reordered after an incomming message. This patch ensures that any stalled message stays in its original request order.
2015-07-20mem: add request types for acquire and releaseDavid Hashe
Add support for acquire and release requests. These synchronization operations are commonly supported by several modern instruction sets.
2015-07-20ruby: allocate a block in CacheMemory without updating LRU stateDavid Hashe
2015-07-20ruby: speed up function used for cache walksDavid Hashe
This patch adds a few helpful functions that allow .sm files to directly invalidate all cache blocks using a trigger queue rather than rely on each individual cache block to be invalidated via requests from the mandatory queue.
2015-07-20slicc: support for arbitrary DPRINTF flags (not just RubySlicc)David Hashe
This patch allows DPRINTFs to be used in SLICC state machines similar to how they are used by the rest of gem5. Previously all DPRINTFs in the .sm files had to use the RubySlicc flag.
2015-07-20slicc: support for local variable declarations in action blocksDavid Hashe
2015-07-20ruby: initialize replacement policies with their own simobjsDavid Hashe
this is in preparation for other replacement policies that take additional parameters.
2015-07-20ruby: give access to cache tag/data latencies from SLICCDavid Hashe
This patch exposes the tag and data array latencies to the SLICC state machines so that it can be used to determine the correct enqueue latency for response messages.
2015-07-20slicc: support for multiple cache entry types in the same state machineDavid Hashe
To have multiple Entry types (e.g., a cache Entry type and a directory Entry type), just declare one of them as a secondary type by using the pair 'main="false"', e.g.: structure(DirEntry, desc="...", interface="AbstractCacheEntry", main="false") { ...and the primary type would be declared: structure(Entry, desc="...", interface="AbstractCacheEntry") {
2015-07-20slicc: Fix bug in enqueue and peek statements.David Hashe
These were not generating the correct c names for types declared within a machine scope.
2015-07-20slicc: fix missing inline function in LocalVariableASTDavid Hashe
2015-07-20slicc: improve support for prefix operationsDavid Hashe
This patch fixes the type handling when prefix operations are used. Previously prefix operators would assume a void return type, which made it impossible to combine prefix operations with other expressions. This patch allows SLICC programmers to use prefix operations more naturally.
2015-07-20slicc: support for transitions with a wildcard next stateDavid Hashe
This patches adds support for transitions of the form: transition(START, EVENTS, *) { ACTIONS } This allows a machine to collapse states that differ only in the next state transition to collapse into one, and can help shorten/simplfy some protocols significantly. When * is encountered as an end state of a transition, the next state is determined by calling the machine-specific getNextState function. The next state is determined before any actions of the transition execute, and therefore the next state calculation cannot depend on any of the transition actions.
2015-07-20slicc: support for multiple message types on the same bufferDavid Hashe
This patch allows SLICC protocols to use more than one message type with a message buffer. For example, you can declare two in ports as such: in_port(ResponseQueue_in, ResponseMsg, responseFromDir, rank=3) { ... } in_port(tgtResponseQueue_in, TgtResponseMsg, responseFromDir, rank=2) { ... }
2015-08-01slicc: fatal->panic on invalid transitionsBrad Beckmann
2015-07-20mem: Hit callback delay fixDavid Hashe
This patch was created by Bihn Pham during his internship at AMD. There is no need to delay hit callback response messages by a cycle because the response latency is already incurred in the Ruby protocol. This ensures correct timing of memory instructions.
2015-07-20cpu: Fixed a bug on where to fetch the next instruction fromDavid Hashe
Figure out if the next instruction to fetch comes from the micro-op ROM or not. Otherwise, wrong instructions may be fetched.
2015-07-20x86: x86 instruction-implementation bug fixesDavid Hashe
Added explicit data sizes and an opcode type for correct execution.
2015-07-20ruby: re-added the addressToInt slicc interface functionBrad Beckmann
This helper function is very useful converting address offsets to integers that can be used for protocol specific destination mapping.
2015-07-20syscall: Add readlink to x86 with special case /proc/self/exeDavid Hashe
This patch implements the correct behavior.
2015-07-20ruby: add useful dprints to sequencerBrad Beckmann
Added two data block dprints that are useful when tracking down data check failures in the ruby random tester.
2015-07-20slicc: isinstance bugfixDavid Hashe
This fix prevents spurious errors when searching for a symbol that may be located in one of multiple symbol tables.
2015-07-31cpu: Update debug message from Fetch1 isDrained() in MinorAndreas Sandberg
Fix a spurious %s and include the state of the Fetch1 stage in the debug printout.
2015-07-31cpu: Fix Minor drain issues when switched outAndreas Sandberg
The Minor CPU currently doesn't drain properly when it is switched out. This happens because Fetch 1 expects to be in the FetchHalted state when it is drained. However, because the CPU is switched out, it is stuck in the FetchWaitingForPC state. Fix this by ignoring drain requests and returning DrainState::Drained from MinorCPU::drain() if the CPU is switched out. This is always safe since a switched out CPU, by definition, doesn't have any instructions in flight.
2015-07-30cpu: Only activate thread 0 in Minor if the CPU is activeAndreas Sandberg
Minor currently activates thread 0 in startup() to work around an issue where activateContext() is called from LiveProcess before the process entry point is known. When activateContext() is called, Minor creates a branch instruction to the process's entry point. The first time it is called, the branch points to an undefined location (0). The call in startup() updates the branch to point to the actual entry point. When instantiating a switched out Minor CPU, it still tries to activate thread 0. This is clearly incorrect since a switched out CPU can't have any active threads. This changeset adds a check to ensure that the thread is active before reactivating it.
2015-07-30cpu: Fix drain issues in the Minor CPUAndreas Sandberg
The drain refactor patches introduced a couple of bugs in the way Minor handles draining. This patch fixes an incorrect assert and a case of infinite recursion when the CPU signals drain done.
2015-07-30mem: Add missing clean eviction on uncacheable accessAndreas Hansson
This patch adds a missing clean eviction, occuring when an uncacheable access flushes and invalidates an existing block.
2015-07-30mem: Remove unused RequestCause in cacheAndreas Hansson
This patch removes the RequestCause, and also simplifies how we schedule the sending of packets through the memory-side port. The deassertion of bus requests is removed as it is not used.
2015-07-30mem: Make caches way awareDavid Guillen-Fandos
This patch makes cache sets aware of the way number. This enables some nice features such as the ablity to restrict way allocation. The implemented mechanism allows to set a maximum way number to be allocated 'k' which must fulfill 0 < k <= N (where N is the number of ways). In the future more sophisticated mechasims can be implemented.
2015-07-30mem: Transition away from isSupplyExclusive for writebacksAndreas Hansson
This patch changes how writebacks communicate whether the line is passed as modified or owned. Previously we relied on the isSupplyExclusive mechanism, which was originally designed to avoid unecessary snoops. For normal cache requests we use the sharedAsserted mechanism to determine if a block should be marked writeable or not, and with this patch we transition the writebacks to also use this mechanism. Conceptually this is cleaner and more consistent.
2015-07-30mem: Tidy up CacheBlk classAndreas Hansson
This patch modernises and tidies up the CacheBlk, removing dead code.
2015-07-30mem: Tidy up packetAndreas Hansson
Some minor fixes and removal of dead code. Changing the flags to be enums rather than static const (to avoid any linking issues caused by the latter). Also adding a getBlockAddr member which hopefully can slowly finds its way into caches, snoop filters etc.
2015-07-30cpu: Fix issue identified by UBSanAndreas Hansson
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
This adds a vector register type. The type is defined as a std::array of a fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now.
2015-07-26cpu: o3: slight correction to identation in rename_impl.hhNilay Vaish
2015-07-24style: change Process function calls to use camelCaseBrandon Potter
The Process class methods were using an improper style and this subsequently bled into the system call code. The following regular expressions should be helpful if someone transitions private system call patches on top of these changesets: s/alloc_fd/allocFD/ s/sim_fd(/simFD(/ s/sim_fd_obj/getFDEntry/ s/fix_file_offsets/fixFileOffsets/ s/find_file_offsets/findFileOffsets/
2015-07-24syscall_emul: standardized file descriptor name and add return checks.Brandon Potter
The patch clarifies whether file descriptors are host file descriptors or target file descriptors in the system call code. (Host file descriptors are file descriptors which have been allocated through real system calls where target file descriptors are allocated from an array in the Process class.)
2015-07-24base: refactor process class (specifically FdMap and friends)Brandon Potter
This patch extends the previous patch's alterations around fd_map. It cleans up some of the uglier code in the process file and replaces it with a more concise C++11 version. As part of the changes, the FdMap class is pulled out of the Process class and receives its own file.