gem5 - gem5

Age	Commit message (Expand)	Author
2006-12-13	Split CachePort class into CpuSidePort and MemSidePort	Steve Reinhardt
2006-12-13	fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.	Lisa Hsu
2006-12-12	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2006-12-12	Allow for multiple redirects to happen on a single cycle (only the one for th...	Kevin Lim
2006-12-12	Rename the StaticInst-based (read\|set)(Int\|Float)Reg methods to (read\|set)(In...	Steve Reinhardt
2006-12-12	Get rid of unused lock code.	Steve Reinhardt
2006-12-11	Fix up in case a req hasn't yet been generated for this instruction (if there...	Kevin Lim
2006-12-11	Fix for fetch to use the icache's block size to generate proper access size.	Kevin Lim
2006-12-09	Merge vm1.(none):/home/stever/bk/newmem-head	Steve Reinhardt
2006-12-06	Fix for MIPS_SE/m5.fast compile.	Kevin Lim
2006-12-05	Don't compress data on writebacks unless it's actually necessary.	Steve Reinhardt
2006-12-04	Turn cache MissQueue/BlockingBuffer into virtual object	Steve Reinhardt
2006-12-02	Merge vm1.(none):/home/stever/bk/newmem-head	Steve Reinhardt
2006-12-02	Support better param conversions to/from numeric subclasses.	Steve Reinhardt
2006-12-02	Fix help strings on GenRepl params.	Steve Reinhardt
2006-12-02	Make cache compression policy a runtime virtual thing	Steve Reinhardt
2006-12-02	Fixes for MIPS_SE compiling. Regressions seem to work, but Korey should make...	Kevin Lim
2006-11-29	Change the connecting of the physPort and virtPort to the memory object below...	Kevin Lim
2006-11-28	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2006-11-28	Remove assertion. It's not needed and messes up writebacks when a 2 level ca...	Kevin Lim
2006-11-27	Add TRACING_ON setting for m5.prof.	Steve Reinhardt
2006-11-24	Add no-op versions of ivlb and ivle back in for backwards compatibility.	Steve Reinhardt
2006-11-22	Do a functional access to levels above on a read as a temporary solution for ...	Ron Dreslinski
2006-11-20	Fix typo.	Kevin Lim
2006-11-19	Update Virtual and Physical ports.	Kevin Lim
2006-11-17	Merge zizzer:/bk/newmem	Ron Dreslinski
2006-11-17	Make an initialization pass for the thread context and set the [phys,virt]Por...	Ron Dreslinski
2006-11-16	add warn_once which will print any given warning message	Nathan Binkert
2006-11-16	implement RUSAGE_CHILDREN for getrusage since it's trivial	Nathan Binkert
2006-11-16	Implement current working directory for LiveProcesses	Nathan Binkert
2006-11-14	Merge zizzer:/bk/newmem	Ron Dreslinski
2006-11-14	Various fixes to delete packet and request a little better.	Kevin Lim
2006-11-14	Merge zizzer:/bk/newmem	Ron Dreslinski
2006-11-14	Fix bugs around uni-coherence invalidates being propogated properly.	Ron Dreslinski
2006-11-14	Merge zizzer:/bk/newmem	Lisa Hsu
2006-11-14	interrupts.hh:	Lisa Hsu
2006-11-14	If all the targets aren't satisfied, reinitialize the packet.	Ron Dreslinski
2006-11-14	Update atomic and functional paths for snoops as well	Ron Dreslinski
2006-11-14	Update phase param in the .py file for the cpus	Ron Dreslinski
2006-11-14	Update bus bridges now that snoop ranges are passed properly	Ron Dreslinski
2006-11-14	Make cpu's capable of having a phase shift	Ron Dreslinski
2006-11-13	Fix a bug to handle the fact that a CPU can send Functional accesses while a ...	Ron Dreslinski
2006-11-13	If we didn't satisfy all targets, reset the packet we are requesting with.	Ron Dreslinski
2006-11-13	Fix some errors related to snooping and functional access in the bus	Ron Dreslinski
2006-11-13	Fix problems with snoop ranges not working properly on functional accesses	Ron Dreslinski
2006-11-13	Changes needed for a bus from CPU->L1	Ron Dreslinski
2006-11-13	Since cpus now send out snoop ranges, remove it from the cache.	Ron Dreslinski
2006-11-13	Make CPU models signal to update the snoop ranges	Ron Dreslinski
2006-11-13	Expose debugBreakCycle through swig and get rid of	Nathan Binkert
2006-11-13	Merge ktlim@zizzer:/bk/newmem	Kevin Lim