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2018-10-26arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}Giacomo Travaglini
According to the arm arm, a SYS instruction (op0 = 1) with CRn = (11 or 15) is implementation defined; this makes it trappable by having HCR_EL2.TIDCP = 1. Change-Id: Idd94ac345fee652ee6f8c0a7eb7b06ac75ec38ef Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13780 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPLGiacomo Travaglini
While there is a AArch32 class for instructions accessing implementation defined registers, we are lacking for the AArch64 counterpart. we were relying on FailUnimplemented, which is untrappable at EL2 (except for HCR_EL2.TGE) since it is just raising Undefined Instruction. Change-Id: I923cb914658ca958af031612cf005159707b0b4f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13779 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Refactor AArch64 MSR/MRS trappingGiacomo Travaglini
This patch refactors AArch64 MSR/MRS trapping, by moving the trapping helpers in arch/arm/utility and in the isa code into a MiscRegOp64 class. This class is the Base class for a generic AArch64 instruction which is making use of system registers (MiscReg), like MSR,MRS,SYS. The common denominator or those instruction is the chance that the system register access is trapped to an upper Exception level. MiscRegOp64 is providing that feature. What do we gain? Other "pseudo" instructions, like access to implementation defined registers can inherit from this class to make use of the trapping functionalities even if there is no data movement between GPRs and system register. Change-Id: I0924354db100de04f1079a1ab43d4fd32039e08d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13778 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Trap to EL2 only if not in Secure StateGiacomo Travaglini
MRS/MSR Instructions should trap to EL2 only if we are in non-Secure state since at the current implementation (Armv8.0) there is no Secure EL2. Change-Id: I93af415fbcbd19a470752adf6afc92e520e9645d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13777 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: Fix HVC trapping beahviourGiacomo Travaglini
This patch is fixing HVC trapping behaviour, reusing the pseudocode implementation provided in the arm arm. Change-Id: I0bc81478400b99d84534c1c8871f894722f547c5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13776 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1Giacomo Travaglini
According to the arm arm, CPTR_EL3.TCPAC traps EL2 accesses to the CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR, are trapped to EL3, unless they are trapped by CPTR_EL2.TCPAC. Change-Id: I637be35b29db39f044dda0c6cc4fe986c9620371 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13775 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-26tests: Convert AddrRangeMap unit test to a GTestAndreas Sandberg
Change-Id: Ifeb0b57c0cda77706691286f78325e50edb31c0d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13736 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-10-26tests: Convert CircleBuf unit test to a GTestAndreas Sandberg
Change-Id: I028c6b8d8e0ec06cac3d636689ae647f717096cd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13735 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-10-22mem-cache: Move evictBlock(CacheBlk*, PacketList&) to baseDaniel R. Carvalho
Move evictBlock(CacheBlk*, PacketList&) to base cache, as it is both sub-classes implementations are equal. Change-Id: I80fbd16813bfcc4938fb01ed76abe29b3f8b3018 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13656 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-19python: Add utility function to override config parametersCiro Santilli
Add a utility method, SimObject.apply_config that can be used to implement SimObject param overrides from the command line. This function provides safe and convenient semantics for CLI assignment: * The override expression is evaluated in a restricted environment. The only global variables are the child objects and params from the root object. * Only params can be overridden. For example, calling methods or setting attributes on SimObjects isn't possible. * Vectors use non-standard list semantics which enable something similar to glob expansion on the shell. For example, setting: root.system.cpu[0:2].numThreads = 2 will override numThreads for cpu 0 and 1 and: root.system.cpus[0,2].numThreads = 2 sets it for cpus 0 and 2. The intention is that the helper method is called to override default values before calling m5.instantiate. Change-Id: I73f99da21d6d8ce1ff2ec8db2bb34338456f6799 Reviewed-on: https://gem5-review.googlesource.com/c/12984 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-19arm: treat aarch64 hints as NOPs instead of panicCiro Santilli
Change-Id: Ida2a746e6188171bd2e4da92a4efb33fcbaa2b69 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13476 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-19arm: update hint instruction decoding to match ARMv8.5Ciro Santilli
This fixes: - unallocated hints that have since been allocated - unallocated and unimplemented hint instructions being treated as Unknown instead of the correct NOP - missing encoding for DBG on A32 Unallocated and unimplemented hints give a warning if executed. The most important fix was for the CSDB Spectre mitigation instruction, which was added recently and previously unallocated and treated as Unknown. The Linux kernel v4.18 ARMv7 uses CSDB it and boot would fail with "undefined instruction" since Linux commit 1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613 Change-Id: I283da3f08a9af4148edc6fb3ca2930cbb97126b8 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13475 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-18mem-cache: Fix unused variable warning in FALRU:invalidate()Nikos Nikoleris
Change-Id: I3b902045433ca56b3e62c251158e784b5fa9e4d7 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13600 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-10-18mem: Add write coalescing and write-no-allocate to the cachesNikos Nikoleris
Enable the cache to detect contiguous writes and hold on to the MSHR long enough to allow the entire line to be written. If the whole line is written, the MSHR will be sent out as an invalidation requests, as it is part of a whole-line write, i.e. no-fetch-on-write. The cache is also able to switch to a write-no-allocate policy on the actual completion of the writes, and instead use the tempBlock and turn the write operation into a writeback. These policies are all well-known, and described in works such as Jouppi, Cache Write Policies and Performance, vol 21, no 2, ACM, 1993. Change-Id: I19792f2970b3c6798c9b2b493acdd156897284ae Reviewed-on: https://gem5-review.googlesource.com/c/12907 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Delay servicing an MSHR after its allocationNikos Nikoleris
An MSHR is allocated and the computed latency determines when the MSHR will be ready and can be serviced by the cache. This patch adds a function that allows changing the time that an MSHR is ready and adjusts the queue such that other MSHRs can be serviced first if they are ready. Change-Id: Ie908191fcb3c2d84d4c6f855c8b1e41ca5881bff Reviewed-on: https://gem5-review.googlesource.com/c/12906 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Restructure whole-line writes to simplify write mergingNikos Nikoleris
This patch changes how we deal with whole-line writes their responses. With these changes, we use the MSHR tracking to determine if a whole-line is written, and on a fill we simply handle the invalidation response, with the actual writes taking place as part of satisfying the CPU-side hit. Change-Id: I9a18e41a95db3c20b97f8bca7d95ff33d35a578b Reviewed-on: https://gem5-review.googlesource.com/c/12905 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Determine if an MSHR does a whole-line writeNikos Nikoleris
This patch adds support for determining whether the targets in an MSHR are 1) only writes and 2) whether these writes are effectively a whole-line write. This patch adds the necessary functions in the MSHR to allow for write coalescing in the cache. Change-Id: I2c9a9a83d2d9b506a491ba5b0b9ac1054bdb31b4 Reviewed-on: https://gem5-review.googlesource.com/c/12904 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Mark the guest endianness packet accessors as deprecated.Gabe Black
Change-Id: Iebefeb5b1ce905f2b45b30b7656d6a01d0724584 Reviewed-on: https://gem5-review.googlesource.com/c/13575 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-10-18null: Stop specifying an endianness in isa_traits.hh.Gabe Black
The NULL ISA doesn't really have an endianness. Now that the packet accessors which consumed that endianness are gone, we can get rid of that setting as well. Change-Id: I8dd4c7b8236b07df4458fea377865f30141121d4 Reviewed-on: https://gem5-review.googlesource.com/c/13466 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-18mem: Explicitly specify the endianness in the abstract memory.Gabe Black
The accessors are used for debugging output. If we're using an ISA where there's an endianness, we use that explicitly, falling back to a binary dump if the size isn't supported. If not, then we just dump the data without interpretation regardless of size. Change-Id: Ib050c4c876ee41f17cfd14ad657150bf6ab1de39 Reviewed-on: https://gem5-review.googlesource.com/c/13464 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-17gpu-compute: Explicitly use little endian packet accessors.Gabe Black
The gpu ISA doesn't have a well defined endianness, but it really should. It seems that the GPU is only used with x86, and in that context it would be little endian. Change-Id: I1620906564a77f44553fbf6d788866e017b6054b Reviewed-on: https://gem5-review.googlesource.com/c/13463 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-10-17arch: Include some additional headers in arch/generic/mmapped_ipr.cc.Gabe Black
These had been included transitively before. Change-Id: Ie420bc957e9abb5cd01fcf720fc1fda619d210f0 Reviewed-on: https://gem5-review.googlesource.com/c/13538 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Remove using namespace TheISA in uart8250.cc.Gabe Black
Nothing in that file is in the TheISA namespace, so there's no reason to use using on it. Change-Id: I279c27af86509f75ac4e340956381041a0dbcdc4 Reviewed-on: https://gem5-review.googlesource.com/c/13537 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Explicitly specify the endianness for packet accessors.Gabe Black
Generally speaking, the endianness of the data devices provide or accept is dependent on the device and not the ISA the system executes. This change makes the devices in dev pick an endianness rather than using the guest's. For the ISA bus and the UART, accesses are byte sized and so endianness doesn't matter. The ISA and PCI busses and the devices which use them are defined to be little endian. Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f Reviewed-on: https://gem5-review.googlesource.com/c/13462 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17python: Stop conditionally excluding code from pyobject.ccGabe Black
Now that the Ether* classes are included in all builds, there's no reason to conditionally compile code in pyobject.cc. Change-Id: If94602af71774b1f090a3344a633207f4b37d308 Reviewed-on: https://gem5-review.googlesource.com/c/13470 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Build most of the networking devices in the NULL_ISA build.Gabe Black
The only part of these devices which are incompatible with other ISAs, with the possible exception of endianness transformation, is that the dist_iface implementation refers to ThreadContext methods and that class is heavily tied to the guest ISA. Only those few lines are excluded in a NULL_ISA build. Change-Id: Ic6d643fdbb792d0a996a37d75e027c5ce0ecd460 Reviewed-on: https://gem5-review.googlesource.com/c/13469 Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Build the PCI device models even in NULL_ISA builds.Gabe Black
There are some minor ISA dependencies in the PCI device models, specifically that they use the set<> accessors on the packet objects. This actually compiles fine because the NULL ISA claims to be little endian, but really these accessors should be changed to use little endian all the time since that's what PCI is defined to use, not the guest endianness. The other types of accessors, specifically the ones that default to what the guest wants, should be excluded when building NULL_ISA, and, pending other dependencies, the NULL_ISA should no longer have an endianness associated with it. Change-Id: I0739122dbf67d109e7959553a1eff0239b090ca4 Reviewed-on: https://gem5-review.googlesource.com/c/13468 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17arch: Get rid of the unused type AnyReg.Gabe Black
This type is defined for all the ISAs but isn't used by anything. Change-Id: I659a0c5abc7883d82fedd1cac2cd103612d315c8 Reviewed-on: https://gem5-review.googlesource.com/c/13539 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev-arm: Don't panic when EOIR a non active PPIAdrien Pesle
GIC architecture specification says that writing EOIR with a not active irq it is an unpredictable behavior. So, just warn when it happens for a PPI case, like it is already done in SPI case. Change-Id: Icb1b8f5690d5e87b15c3b0fe2ca0d37fdd4085ee Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13556 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev-arm: Fix Gicv2 distributor group registerAdrien Pesle
For each bit in GICD_IGROUPR: value 0 means corresponding irq is group0 value 1 means corresponding irq is group 1. Change-Id: I15699d4bc89ff3df0e0bdb41154c0d0989dc2f63 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13555 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-16systemc: Get rid of leftovers from unimplemented warnings past.Gabe Black
These warnings were removed when the functionality they warned about was implemented, but there were some leftovers like unnecessary includes and some helper functions which hid gem5 specific headers from the ext directory. Change-Id: Ic886ac0f1264687524e3a7b7eaab8836f318a5a2 Reviewed-on: https://gem5-review.googlesource.com/c/13398 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Implement Object::simcontext().Gabe Black
Implement it as a nonstandard alias for the also non-standard sc_get_curr_simcontext. Change-Id: Ic9a51efa93f687e4b57d622247a5510136fab221 Reviewed-on: https://gem5-review.googlesource.com/c/13397 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Stop filtering out warnings about unimplemented features.Gabe Black
These no longer cause any of the tests to break, so there's no reason to filter them out. Change-Id: I9c0b25fc42eb3060ac7d6d6a46ded130227c302d Reviewed-on: https://gem5-review.googlesource.com/c/13396 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Warn about using deprecated sc_port constructors.Gabe Black
This gets rid of one of the last instances of a warning about unimplemented functionality. Change-Id: I3d8e50ea45554cba969118ce873ed3d2b041ec43 Reviewed-on: https://gem5-review.googlesource.com/c/13395 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Add a python config class for sc_modules.Gabe Black
This class doesn't really add anything, but it provides a consistent base class for sc_modules vs. generic sc_objects. Change-Id: I3fbd4f6b5d1be0b5419f5cbd304aec61d404a341 Reviewed-on: https://gem5-review.googlesource.com/c/13355 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Don't include the scheduler in an external header file.Gabe Black
The scheduler is an internal detail and shouldn't be exposed to the headers in ext. It would transitively include more headers which are not in ext, making it not self contained. Change-Id: I8384cde9d19363953ffd0c91e7d8d27f8f79a570 Reviewed-on: https://gem5-review.googlesource.com/c/13336 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Add an accessor for getting the current process.Gabe Black
This is to avoid having to expose the scheduler (which tracks the current process) to header files which should be independent of gem5 and the underlying implementation. Change-Id: I1b0810ab66c3ce52b5b94236d7df86da66a62472 Reviewed-on: https://gem5-review.googlesource.com/c/13335 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Don't re-schedule a process which is already scheduled.Gabe Black
Change-Id: I8e12713c49aad03d0bfb779883adcbfa8fd4b42e Reviewed-on: https://gem5-review.googlesource.com/c/13334 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Fix accounting in the sc_fifo class.Gabe Black
Reads shouldn't free up space until an update happens. Change-Id: I18e1601c27b44643f103c86f04b1fa2c23baf1e8 Reviewed-on: https://gem5-review.googlesource.com/c/13333 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Exclude a test which tests a feature we're not implementing.Gabe Black
Change-Id: Ieaca025786d70c0d851eec9d1eb9f7f01b513cde Reviewed-on: https://gem5-review.googlesource.com/c/13332 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Switch to using predefined messages for datatypes.Gabe Black
Create and use predefined messages for datatypes which match the ones Accellera uses. Change-Id: I92dd52f62462b864264217bb81f3ff1dcec020bf Reviewed-on: https://gem5-review.googlesource.com/c/13331 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Switch to using predefined messages for channels.Gabe Black
Create and use predefined messages for channels which match the ones Accellera uses. Change-Id: I179214838bbd83604e50225926cdc6b5b1b16923 Reviewed-on: https://gem5-review.googlesource.com/c/13330 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Don't depend on the order of static initializers.Gabe Black
STL containers may need to be constructed before they're used. Don't count on being able to insert into them during a static initializer. Change-Id: Icb05d5084a470e1ebd976ae6e1954b1a78aabd6a Reviewed-on: https://gem5-review.googlesource.com/c/13329 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Switch to using predefined messages for utils.Gabe Black
Create and use predefined messages for utils which match the ones Accellera uses. Change-Id: I932b7206fc16181d01a0d5b7441ce617b30e5365 Reviewed-on: https://gem5-review.googlesource.com/c/13328 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Remove a redundant error check.Gabe Black
If the check doesn't abort the port binding in progress, it will be reported twice. Change-Id: I691ebd0f1598193f861c6085341dcd2fb05dd210 Reviewed-on: https://gem5-review.googlesource.com/c/13327 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Check the maximum port size when finializing bindings.Gabe Black
Change-Id: Ie7d704547bb8523a3c44479a89d2af4fcce6e8b6 Reviewed-on: https://gem5-review.googlesource.com/c/13326 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Fix how the maximum size is computed for sc_ports.Gabe Black
Change-Id: I073eb16cbeb892f24ac3860daca056ed2fb09086 Reviewed-on: https://gem5-review.googlesource.com/c/13325 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Mark a test as expected to fail.Gabe Black
This test expects to exit with an error. Change-Id: Id0b1ae4967ad0b8a356c7a04ed5fe9eb2f3c6641 Reviewed-on: https://gem5-review.googlesource.com/c/13324 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Switch to using predefined messages for core.Gabe Black
Create and use predefined messages for core which match the ones Accellera uses. Change-Id: I05b1398933f753946d5917f39d0f39c7cb45ed9f Reviewed-on: https://gem5-review.googlesource.com/c/13323 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-16systemc: Add a mechanism for pre-registering message type ids.Gabe Black
These ids are the ones the Accellera implementation/tests use. Some of the tests expect them to be available and usable. Change-Id: I4e4dc3470c28d4113330a44ccd06ffe7724e75b1 Reviewed-on: https://gem5-review.googlesource.com/c/13322 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
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