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AgeCommit message (Expand)Author
2015-03-02cpu: Add a PC-value to the traffic generator requestsStephan Diestelhorst
2015-03-02arm: Don't truncate 16-bit ASIDs to 8 bitsAndreas Sandberg
2015-03-02arm: Correctly access the stack pointer in GDBAndreas Sandberg
2015-03-02arm: Fix broken page table permissions checks in remote GDBAndreas Sandberg
2015-02-26Ruby: Update backing store option to propagate through to all RubyPortsJason Power
2015-02-16cpu: TrafficGen sinks snoops without complainingAndreas Hansson
2015-02-16mem: Fix initial value problem with MemCheckerStephan Diestelhorst
2015-02-16dev: Fix undefined behaviuor in i8254xGBeAndreas Hansson
2015-02-16arm: Wire up the GIC with the platform in the base classAndreas Sandberg
2015-02-16mem: mmap the backing store with MAP_NORESERVEAndreas Hansson
2015-02-16mem: Use the range cache for lookup as well as accessAndreas Hansson
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
2015-02-16arm: Merge ISA files with pseudo instructionsAndreas Sandberg
2015-02-16cpu: add support for outputing a protobuf formatted CPU traceAli Saidi
2015-02-11mem: Clarification of packet crossbar timingsMarco Balboni
2015-02-11mem: Clarify usage of latency in the cacheMarco Balboni
2015-02-11cpu: Tidy up the MemTest and make false sharing more obviousAndreas Hansson
2015-02-11sim: Move the BaseTLB to src/arch/generic/Andreas Sandberg
2015-02-11base: Add compiler macros to add deprecation warningsAndreas Sandberg
2015-02-11base: Do not dereference NULL in CompoundFlag creationAndreas Hansson
2015-02-11dev: Remove unused system pointer in the Platform base classAndreas Sandberg
2015-02-06cpu: Idle CPU status logic revisedAlexandru Dutu
2015-02-03mem: Clarify express snoop behaviourAndreas Hansson
2015-02-03mem: Clarify cache behaviour for pending dirty responsesAndreas Hansson
2015-02-03base: add an accessor and operators ==,!= to address rangesCurtis Dunham
2015-02-03base: Add XOR-based hashed address interleavingAndreas Hansson
2015-02-03config: Adjust DRAM channel interleaving defaultsAndreas Hansson
2015-02-03sim: Remove test for non-NULL this in EventAndreas Sandberg
2015-02-03dev: Correctly clear interrupts in VirtIO PCIAndreas Sandberg
2014-12-19sim: prioritize async events; prevent starvationCurtis Dunham
2015-02-03cpu: Ensure timing CPU sinks response before sending new requestAndreas Hansson
2015-02-03config: Fix typo in Float paramGeoffrey Blake
2015-01-25arm: always set the IsFirstMicroop flagAli Saidi
2015-01-25sim: Clean up InstRecordAli Saidi
2015-01-25cpu: Remove all notion that we know when the cpu is misspeculating.Ali Saidi
2015-01-25cpu: Put all CPU instruction tracers in a single fileAli Saidi
2015-01-25cpu: remove legion tracerAli Saidi
2014-12-23sim: fix reference counting of PythonEventCurtis Dunham
2015-01-22mem: Remove unused Packet src and dest fieldsAndreas Hansson
2015-01-22mem: Remove Packet source from ForwardResponseRecordAndreas Hansson
2015-01-22mem: Remove unused RequestState in the bridgeAndreas Hansson
2015-01-22mem: Always use SenderState for response routing in RubyPortAndreas Hansson
2015-01-22mem: Make the XBar responsible for tracking response routingAndreas Hansson
2015-01-22x86: Delay X86 table walk on receiving walker responseAndreas Hansson
2015-01-22mem: Clean up Request initialisationAndreas Hansson
2015-01-20cpu: commit probe notification on every microop or macroopNikos Nikoleris
2015-01-20mem: Fix bug in cache request retry mechanismAndreas Hansson
2015-01-20cpu: Fix retry bug in MinorCPU LSQAndreas Hansson
2015-01-20mem: Move DRAM interleaving check to initAndreas Hansson
2015-01-10x86 : fxsave and fxrestore missing template codeEmilio Castillo
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