gem5 - gem5

Age	Commit message (Expand)	Author
2019-01-22	sim-se add readv and modifies writev	Brandon Potter
2019-01-22	sim-se: add ability to get/set sock metadata	Brandon Potter
2019-01-22	sim-se: add syscalls related to polling	Brandon Potter
2019-01-22	sim-se: add calls for network transmissions	Brandon Potter
2019-01-22	sim-se: add socket-based functionality	Brandon Potter
2019-01-18	base: Fix unitialized storage	Daniel R. Carvalho
2019-01-17	mem: Allow inserts in the begining of a packet queue	Nikos Nikoleris
2019-01-17	mem: Determine if a packet queue forces ordering at construction	Nikos Nikoleris
2019-01-17	cpu-o3: Make the smtCommitPolicy a Param.ScopedEnum	Nikos Nikoleris
2019-01-17	cpu-o3: Make the smtROBPolicy a Param.ScopedEnum	Nikos Nikoleris
2019-01-17	cpu-o3: Make the smtIQPolicy a Param.ScopedEnum	Nikos Nikoleris
2019-01-17	cpu-o3: Make the smtLSQPolicy a Param.ScopedEnum	Nikos Nikoleris
2019-01-17	cpu-o3: Make the smtFetchPolicy a Param.ScopedEnum	Nikos Nikoleris
2019-01-17	python: Add support for scoped enums	Nikos Nikoleris
2019-01-16	cpu: dev: sim: gpu-compute: Banish some ISA specific register types.	Gabe Black
2019-01-16	arch: Make the ISA register types aliases for the global types.	Gabe Black
2019-01-16	arm: Make the fp register types 64 bits.	Gabe Black
2019-01-16	mem-cache: Access Map Pattern Matching Prefetcher	Javier Bueno
2019-01-16	mem-cache: Signature Path Prefetcher	Javier Bueno
2019-01-16	mem-cache: allow prefetchers to emit page crossing references	Javier Bueno
2019-01-16	mem-cache: virtual address support for prefetchers	Javier Bueno
2019-01-16	arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled	Giacomo Travaglini
2019-01-16	arch-arm: Added TLBI_ALL EL2 instruction	Anouk Van Laer
2019-01-16	arch-riscv: Add interrupt handling	Alec Roelke
2019-01-16	arch-riscv: Fix reset function and style	Alec Roelke
2019-01-15	cpu: Fix usage of setArchVecElem	Giacomo Travaglini
2019-01-15	arch-arm: Fix usage of RegId constructor for VecElem	Giacomo Travaglini
2019-01-14	arm: Stop using the FloatReg and FloatRegBits types.	Gabe Black
2019-01-14	config: De-nest the code in Port.splice().	Gabe Black
2019-01-14	config: Fix an error message in Port.splice().	Gabe Black
2019-01-11	misc: updated shabang for python script	Andrea Mondelli
2019-01-10	sim-se, arch-arm: Add support for getdents64	Javier Setoain
2019-01-10	arch-arm, sim-se: Add support for TLS in clone	Andreas Sandberg
2019-01-10	arch-arm, sim-se: Fix incorrect SP handling in clone	Andreas Sandberg
2019-01-10	sim-se: Refactor clone to avoid most ifdefs	Andreas Sandberg
2019-01-10	sim-se: Correctly calculate next PC in clone	Andreas Sandberg
2019-01-10	sim-se: Use CONFIG_CLONE_BACKWARDS for Arm	Andreas Sandberg
2019-01-10	arch-arm, sim-se: Wire up syscalls needed for pthreads	Javier Setoain
2019-01-10	dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 support	Jairo Balart
2019-01-10	dev-arm: Add a GICv3 model	Jairo Balart
2019-01-10	base: Make it possible to convert strings to enums	Giacomo Travaglini
2019-01-10	systemc: Fix a function which was broken during style fixes.	Gabe Black
2019-01-09	arch-arm: Additional bits in misc ARM registers to use with the TLB and page ...	Ivan Pizarro
2019-01-09	systemc: Make input.txt a dependency for the tlm/endian_conv test.	Gabe Black
2019-01-09	systemc: Exclude some failing systemc TLM tests in working.filt.	Gabe Black
2019-01-09	systemc: Remove the TLM dependence on a non-standard method.	Gabe Black
2019-01-09	systemc: Stop using the sc_string_view type.	Gabe Black
2019-01-09	systemc: Replace sc_core::sc_type_index with std::type_index.	Gabe Black
2019-01-09	systemc: Stop using the Accellera specific "none" global event object.	Gabe Black
2019-01-09	systemc: Rename tlm_core header files to have a .hh extentension.	Gabe Black