gem5 - gem5

Age	Commit message (Expand)	Author
2015-01-22	mem: Remove Packet source from ForwardResponseRecord	Andreas Hansson
2015-01-22	mem: Remove unused RequestState in the bridge	Andreas Hansson
2015-01-22	mem: Always use SenderState for response routing in RubyPort	Andreas Hansson
2015-01-22	mem: Make the XBar responsible for tracking response routing	Andreas Hansson
2015-01-22	x86: Delay X86 table walk on receiving walker response	Andreas Hansson
2015-01-22	mem: Clean up Request initialisation	Andreas Hansson
2015-01-20	cpu: commit probe notification on every microop or macroop	Nikos Nikoleris
2015-01-20	mem: Fix bug in cache request retry mechanism	Andreas Hansson
2015-01-20	cpu: Fix retry bug in MinorCPU LSQ	Andreas Hansson
2015-01-20	mem: Move DRAM interleaving check to init	Andreas Hansson
2015-01-10	x86 : fxsave and fxrestore missing template code	Emilio Castillo
2015-01-10	cpu: fix RetiredStores probe point	Nikos Nikoleris
2015-01-06	dev: prevent intel 8254 timer counter events firing before startup	cdirik
2015-01-07	test: Add a unittest for the BitUnion types.	Gabe Black
2015-01-07	base: Fix assigning between identical bitfields.	Gabe Black
2015-01-06	x86: Enable three bits in the FamilyModelStepping ECX CPUID bitfield.	Gabe Black
2015-01-06	cpuid, x86: Revert "Enabling more features in CPUid"	Gabe Black
2015-01-03	minor: fixed LSQ MasterPortID	Andrew Lukefahr
2015-01-03	arm: Add unlinkat syscall implementation	mike upton
2015-01-03	x86: implements the simd128 ADDSUBPD instruction	Maxime Martinasso
2015-01-03	dev: prevent RTC events firing before startup	Cagdas Dirik
2014-12-27	syscall_emul: Return correct writev value	Joel Hestness
2014-12-23	mem: Change prefetcher to use random_mt	Mitch Hayenga
2014-12-23	mem: Hide WriteInvalidate requests from prefetchers	Curtis Dunham
2014-12-23	mem: Fix event scheduling issue for prefetches	Mitch Hayenga
2014-12-23	mem: Fix bug relating to writebacks and prefetches	Mitch Hayenga
2014-12-23	mem: Rework the structuring of the prefetchers	Mitch Hayenga
2014-12-23	mem: Add parameter to reserve MSHR entries for demand access	Mitch Hayenga
2014-12-23	arm: Add stats to table walker	Curtis Dunham
2014-12-23	config: Expose the DRAM ranks as a command-line option	Andreas Hansson
2014-12-23	mem: Ensure DRAM controller is idle when in atomic mode	Andreas Hansson
2014-12-23	mem: Add rank-wise refresh to the DRAM controller	Omar Naji
2014-12-23	mem: Fix a bug in the DRAM controller arbitration	Omar Naji
2014-12-23	mem: Add stack distance statistics to the CommMonitor	Kanishk Sugand
2014-12-23	mem: Add a stack distance calculator	Kanishk Sugand
2014-12-23	mem: Add MemChecker and MemCheckerMonitor	Marco Elver
2014-12-23	arm: Raise an alignment fault if a PC has illegal alignment	Andreas Sandberg
2014-12-23	arm: Clean up and document decoder API	Andreas Sandberg
2014-12-23	arm: Add support for filtering in the PMU	Andreas Sandberg
2014-12-09	Let other objects set up memory like regions in a KVM VM.	Gabe Black
2014-12-08	arm: Fix decoding of PMXEVTYPER_EL0 and PMCCFILTR_EL0	Andreas Sandberg
2014-12-08	dev: Add response sanity checks in PioPort	Andreas Sandberg
2014-12-08	dev: Correctly transform packets into responses	Andreas Sandberg
2014-12-05	misc: Generalize GDB single stepping.	Gabe Black
2014-12-05	x86: Implement a remote GDB stub.	Gabe Black
2014-12-05	misc: Add some utility functions for schedule inst commit events.	Gabe Black
2014-12-05	misc: Rename the GDB "Event" event class to InputEvent.	Gabe Black
2014-12-05	sim: Ensure GDB interrupts the simulation at an instruction boundary.	Gabe Black
2014-12-05	cpu: Only check for PC events on instruction boundaries.	Gabe Black
2014-12-05	misc: Make the GDB register cache accessible in various sized chunks.	Gabe Black