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2019-05-08mem-cache: Create cache compressorDaniel R. Carvalho
Create basic template for cache compressors. A basic compressor must implement a compression and a decompression method. Change-Id: I83dc4d2b8d2bc5ed9f760c938edfa4ebdd6b8583 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11100 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Add block size to findVictimDaniel R. Carvalho
Add block size to findVictim. For standard caches it will not be used. Compressed caches, however, need to know the size of the compressed block to decide whether a block is co-allocatable or not. Change-Id: Id07f79763687b29f75d707c080fa9bd978a408aa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11198 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Mohammad Seyedzadeh <sm.seyedzade@gmail.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Add compression data to CompressionBlkDaniel R. Carvalho
Add a compression bit, decompression latency and compressed block size and their respective getters and setters. Change-Id: Ia9d8656552d60e8d4e85fe5379dd75fc5adb0abe Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11102 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Create CacheComp debug flagDaniel R. Carvalho
Create a debug flag for cache compression. Change-Id: Id4b8e86d658d3aa550906ee0f8da3b54f4cdab7d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11104 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-08mem-cache: Stub compression frameworkDaniel R. Carvalho
Create a stub of a compression framework where we can have multiple data blocks per tag entry. Only consecutive blocks can share a tag as of now. For each tag entry there can be multiple data blocks. We have the same number of tags a conventional cache would have, but we instantiate the maximum number of data blocks (according to the compression ratio) per tag, to virtually implement compression without increasing the complexity of the simulator. Change-Id: I549940c7afb2f744ab293ff8bb283967e7551a11 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10763 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-07x86: Mark translation as delayed in case of a hw page table walkGabor Dozsa
This information is used by the LSQ in the O3 cpu (since commit "51becd2... cpu-o3: O3 LSQ Generalisation") Change-Id: I35fe7e2f8428641d863af0e79e28b0b259fb0b00 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18508 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-06sim-se: correct statfs inclusion on !linux hostAndrea Mondelli
- Added missing header - Fixed typo on __linux__ macro conditional - s/ifdef/if defined/g for consistency Change-Id: I83b69856e5ec8b23b707642c0e14216cf62db31e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18668 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-04arch-riscv: Implement MHARTID CSRAlec Roelke
This patch implements the MHARTID CSR by intercepting attempts to access it, similar to the way accesses to the performance counters are intercepted, to return the thread's context ID. Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16988 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-03sim-se: fix a few bugs/warns from GCC 6Joe Gross
Change-Id: Ib2ad860324fd234b23262d141be3e82628ff61f0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12126 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-05-03sim-se: add eventfd system callBrandon Potter
Change-Id: I7aeb4fe808d0c8f2fb8041e3662d330d8458f09c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12125 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-05-03mem-cache: Mark block as dirty after a SWPrefetchEXRespNikos Nikoleris
This is a workaround for a bug introduced from the change: 59e3585a8 arch-arm: We add PRFM PST instruction for arm which can cause deadlocks in the memory system. The design of the classic memory system in gem5 makes the folloing two assumptions: * A cache that fetches a block with an intention to modify it, becomes the point of ordering and therefore commits to respond to any snoop requests [1]. * A cache that fetches an exclusive copy of the block, does so with the intention to modify it [2]. Immediately after it receives the block, it will write to it and mark it as dirty. As the point of ordering, it responds to any outstanding snoops. The current implementation of prefetch exclusive request breaks the second assumption. A cache can fetch an exclusive block without an immediate intention to modify it. If the block is not modified, it will not be marked as dirty. However, the cache has committed to respond to outstanding snoops, and if the block is clean it won't. This can result in deadlocks where a snoop gets stuck waiting for responses. One solution (implemented by this patch) is to unconditionally mark the block dirty when filling due to a prefetch exclusive request. This makes the PrefetchExReq behave like a WriteReq. However, as it may mark as dirty a clean block, it creates the requirement for an uncessary WritebackDirty in the future. In practice, this shouldn't be a big problem unless the application is unnecessarily using prefetch exclusive instructions. Other solutions, would require deeper changes to the design of the memory system to handle this properly. [1]: When a cache commits to respond, it "informs" the xbar/PoC (point of coherence) and the other caches of its intention to respond. As a result the request will not be send to the main memory. [2]: In fact the assumption is that in the needsWritable MSHR there is at least one WriteReq before any snoops from other caches. Change-Id: I378d3c0dadf25fc52e430b67102347b44d2f18ea Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17729 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-03arch-riscv,isa: Fix for compressed jump (c_j) immAvishai Tvila
c_j(al) has a special format, called CJ. The jump offset format is instbits[12:2] --> offset[11|4|9:8|10|6|7|3:1|5] Currently in decoder.isa, c_j format is JOp, the imm and branchTarget are incorrect In the execute section (decoder.isa:228), the imm fields is ignored and the offset is calculated correctlly. As a result, we get decoder flush for each c_j instance I've added CJOp format in compressed.isa, and use it in execute section. In addition, c_j is mappped to jal zero, cj_imm, and actually is neither indirect control nor a function call I fixed the flags accordently. I'll fix all IsRet, IsCall and IsIndirectControl flags for rest of (c_)jal(r) in my next commit. I ran coremark -O0 before my fix and I got 37.7% branch miss-rate, after the fix the branch miss-rate is <13% Change-Id: I608d5894a78a1ebefe36f21e21aaea68b42bccfc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17808 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
2019-05-03dev: StreamID generation in DMA deviceGiacomo Travaglini
This patch is adding a StreamID tag to any DMA Packet. StreamIDs are tags which are used by IOMMUs to distinguish between different devices/functions. For PCI devices for example, the RID (Pci Bus number, Pci Device number, Pci Function number) could be stored in the Packet streamID field. For the DmaDevice base class, a simple pair of (Sub)StreamIDs has been provided. This is basically attaching a fixed (decided at python config time) streamID per device. If a derived device wants to implement a more elaborate packet tagger (for example if it wants to have more than one streamID), it needs to pass a different StreamID and SubstreamID to the DmaPort interface (like dmaAction). Change-Id: Ia17cf00437f7d3eb79211c1374134b174f90de59 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16749 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Store a PhysProxy port in Gicv3RedistGiacomo Travaglini
This spares us from retrieving the TC pointer every time we want to write/read to memory (LPIs) Change-Id: Iad76b5e69188fa0ac5c6777a3b2664b0fc66b12f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18600 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Add named variable for GICD_TYPER.IDBitsGiacomo Travaglini
This could be used by other GICv3 components to query the maximum number of implemented interrupt identifiers Change-Id: I132e50de331aea22523260bcefba7e961b53eccd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18599 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Read correct version of ICC_BPR registerGiacomo Travaglini
Some methods like groupPriorityMask check for the value of binary point registers. Those registers have a minimum value. Writing to those register is taking this into account, but the problem with the minimum value arises when the value is checked before sw is writing to them. In this case the minimum value won't be considered if the read is directly forwarded to the ISA class. Change-Id: Id432a37f1634b02bc478d65c52ffb88323d4bb77 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18598 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Get a Gicv3Redistributor ptr from phys addressGiacomo Travaglini
The patch is adding the following method to Gicv3: * Gicv3::getRedistributorByAddr This will be needed by the ITS when trying to select the target redistributor after decoding the collection table entry (RDBase). Change-Id: I40e2c155f2fdc8ca6d3c20ff7a27702e02499f20 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18597 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Add several LPI methods in Gicv3RedistributorGiacomo Travaglini
Refactoring the existing in code in smaller methods will be crucial when adding the ITS module, which is a client for the redistributor class and which will require it to take different actions depending on the command it receives from software. List of methods: * read/writeEntryLPI Reading/Writing a byte from the LPI pending table * isPendingLPI Checks if the pINTID LPI is set. Knowing if an LPI is set is needed by the MOVI command, which is transfering the pending state from one redistributor to the other only if the LPI is pending. Change-Id: If14b1c28ff7f2aa20b12dcd822bf6a490cbe0270 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18596 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Take LPIs into account when interacting with CPUIF regsGiacomo Travaglini
Previous code was not handling LPIs when it came to activation/deactivation of interrupts. Change-Id: Ie38f83c66afdc42132679d7e2e5823990f1710d0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18595 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Fix GICv3 LPIs priority valueGiacomo Travaglini
Priority bits in the LPI configuration table entry are only the MSBits ([7:2]) and need to be shifted in order to get the real LPI priority value. Change-Id: Id04dd4fa9113a32712c73a7094df498de3c0d2b5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18594 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Disable LPI Configuration Table cachingGiacomo Travaglini
This is done since caching is not done correctly, and we don't care for now about performance degradations since the redistributor is using PhysProxy ports. Caching will make sense once the magical accesses will be replaced by real atomic/timing transactions. Change-Id: Iafe2a7843210111efc82c265bd0d5ec3cd9abb5a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18593 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Check EnableLPIs before checking for pending LPIsGiacomo Travaglini
Before reading the tables, GICR_PENDBASER and GICR_PROPBASER need to be properly set, and those will have a consistent value only once sw enables LPIs. Change-Id: Ifb87944a491045e7a13ce7a280c555cb0c1e47f4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18592 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: GICv3 LPI tables are using physical addressesGiacomo Travaglini
Change-Id: I439112f318720ae74c43a374fd3a524c607b3a23 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18591 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Fix GICv3 LPI loopGiacomo Travaglini
Loop was mistakenly increasing the upper bound of the iteration rather than the index variable itself. Change-Id: I0a5a7bc189bc0954a8a6d9581032c2ed902030da Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18590 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Fix Bitwise operation in GICv3Giacomo Travaglini
GICv3 LPI code is wrongly using the xor operator (^) in order to evaluate powers of two. Change-Id: Ib1131fd5940d334967a3741f8fd15d86625be356 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18589 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30arch: Stop using TheISA within the ISAs.Gabe Black
We know for sure what the ISA is, so there's no need for the indirection. Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18488 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30x86: Get rid of some unnecessary TheISA-es in x86.Gabe Black
The X86ISA namespace is already available. Change-Id: I5774968fdfb30b01eba52cdec5e6ef2c75cb66e4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18471 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30sparc: Move translation constants from isa_traits.hh into tlb.hh.Gabe Black
These aren't used outside of SPARC. Also get rid of some unused constants. Change-Id: Icfe119f88189348245a6f225a61e62dfa93ea951 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18470 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.Gabe Black
Those types aren't generic or used outside of SPARC. Change-Id: I9bb154920a9625f12388c3d295dc933ab51fadde Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18469 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30arch: Remove the mt.hh switching header.Gabe Black
This header was only useful in MIPS and is only used internally within MIPS. It doesn't need to be a switching header file. Change-Id: Id7005f73b95e122f9ab83b3b657cae3391682f26 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18468 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30cpu: alpha: Delete all occurrances of the simPalCheck function.Gabe Black
This is now handled within the ISA description. Change-Id: Ie409bb46d102e59d4eb41408d9196fe235626d32 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18434 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30alpha: Implement simPalCheck within the ISA description.Gabe Black
This doesn't need to be plumbed through generic interfaces. If the function/instruction got more complex in the future (unlikely since Alpha doesn't really see development these days), it could be moved to a helper function defined within Alpha files. Change-Id: Ib746fad7bb13c5cc9c6ee555c3a46ce686771c12 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18433 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-30cpu: Remove hwrei from the generic interfaces.Gabe Black
This mechanism is specific to Alpha and doesn't belong sprinkled around the CPU's generic mechanisms. Change-Id: I87904d1a08df2b03eb770205e2c4b94db25201a1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18432 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30sim-se: use DPRINTF_SYSCALL for ioctl/wait4Alexandru Dutu
Change-Id: I4fbaf1a0653f13ae964a2574cc26bbaac2dc0686 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12124 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-04-30sim-se: bugfix for 54c77aa055eBrandon Potter
54c77aa055e introduced a bug which manifests as cyclical dependency on a member initialization for the Process class. The current working directory (cwd) parameter is passed into Process to initialize both the target and host versions of the cwd. (The target and host versions may differ if the faux filesystem is used.) The host cwd init invoked methods which rely on the host cwd already being initialized. To avoid the bug, the code will now rely on using the targets cwd version, but will issue checks against the redirect paths. Change-Id: I4ab644a3e00737dbf249f5d6faf20a26ceb04248 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18448 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
Then cast to the ISA specific type when necessary. This removes (mostly) an ISA specific aspect to some of the interfaces. The ISA specific version of the kernel stats still needs to be constructed and stored in a few places which means that kernel_stats.hh still needs to be a switching arch header, for instance. In the future, I'd like to make the kernel its own object like the Process objects in SE mode, and then it would be able to instantiate and maintain its own stats. Change-Id: I8309d49019124f6bea1482aaea5b5b34e8c97433 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18429 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-30alpha: Implement HWREI in the ISA.Gabe Black
This moves it out of generic interfaces and the CPU implementations. Change-Id: I6767d6b26d0ae128b5bdad5830dce838be74e256 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18431 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30alpha: Add some control registers to the ISA operands list.Gabe Black
These will be used in the in-ISA HWREI implementation. Change-Id: Ia9f7bf1aa2dbd764c878911c2cba680840397c62 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18430 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30sim-se: add socket ioctlsBrandon Potter
The OpenMPI 1.8.2 runtime needs the ioctl code included in this patch to issue socket operations on the host machine. Change-Id: I687b31f375a846f0bab2debd9b9472605a4d2c7d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12123 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-30systemc: Add a distinct async_request_update mechanism.Gabe Black
This mechanism had just been plumbed into the regular request_update, but that doesn't have any thread safety which is the whole point of async_request_update. This new mechanism puts async update requests into their own list which is checked any time normal updates happen. The delta cycle which triggers those updates must happen through some other means which will usually be ok. The exact timing of the update is undefined, so it would be legal for it to either not be recognized before the impending end of the simulation, or for it to get picked up by subsequent activity. If there isn't subsequent activity but the simulation also doesn't end, for instance if there are only gem5 events left, then that update could be lost. That is an unresolved issue. It would be nice to schedule a "ready" event if async updates were added which would ensure they wouldn't starve. Unfortunately that requires the event queue lock, and in practice it's been found that a systemc process might block, effectively holding the event queue lock, while it waits for some asyncrhonous update to give it something to do. This effectively deadlocks the system since the update is blocked on the lock the main thread holds, and the main thread is blocked waiting for the update. Change-Id: I580303db01673faafc2e63545b6a69b3327a521c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18288 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29cpu: Get rid of the (read|set)RegOtherThread methods.Gabe Black
These are implemented by MIPS internally now. Change-Id: If7465e1666e51e1314968efb56a5a814e62ee2d1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18436 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29mips: Implement readRegOtherThread and setRegOtherThread directly.Gabe Black
These accessors can be implemented as helper functions within MIPS without having to plumb them through a bunch of common interfaces. There are a few problems with the way they were implemented which are carried forward to this new implementation as well. That includes hiding the register accesses from the ISA parser and therefore the CPU's dependency tracking, potentially panicing or accessing a non existent thread based on a possible set of input values, and modifying register values even if an instruction is being executed speculatively. Fixing these problems would be fairly involved and require changing how dependencies are tracked in all the CPUs so that they can act across threads, and also how registers are handled in the ISA description itself. The original implementation just punted on making this work in CPUs other than the minor CPU (and potentially one or more CPU models that were not and/or are not in the code base). Where as that implementation might have paniced if these methods were called, this will attempt to work, but may have incorrect behavior based on the limitations described above. I'd consider this an acceptable tradeoff, at least for the time being. Change-Id: I94adceafb9812a8641c76ea3518c3285c31baf51 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18435 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29cpu: Include debug flags regardless of whether the ISA is null.Gabe Black
Whether debug flags are available has no interaction with what the ISA is. Change-Id: I71d9204f948618831796e6c7a4c16bbebfb1a4fb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18428 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29sim-se: create Proc out files in out dirSteve Reinhardt
Redirected output files from Process objects were being created in the current directory instead of in the output directory. Change-Id: Ieb6ab5556fbcc811f4f24910da247d4dcdbc71bd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12122 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29arch-arm: Faults DebugFlag now printing inst opcode if availableGiacomo Travaglini
This makes it easier to debug unimplemented instructions. Change-Id: Iaaa288037326722f07251299fd68eacb2e295376 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18396 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29arch-arm: Report real instruction encoding when UndefinedGiacomo Travaglini
When dumping the opcode that caused an Undefined Instruction, we just want to dump the real instruction encoding, and not the extended version with metabits (like thumb, bigThumb etc). This was not appening when panicking in SE mode. The patch is also replacing custom masking in the Unknown(64) disassembler in favour of ArmStaticInstruction::encoding() helper. Change-Id: I9eb6fd145d02b4b07bb51f0bd89ca014d6d5a6de Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18395 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
The AuxVector type has a bunch of accessors which just give access to the underlying variables through references. We might as well just make those members accessible directly. Also, the AuxVector doesn't need to handle endianness flips itself. We can tell the byteswap mechanism how to flip an AuxVector, and let it handle that for us. This gets rid of the entire .cc file which was complicated by trying to both hide the ISA specific endianness translations, and instantiate templated functions in a .cc. Change-Id: I433cd61e73e0b067b6d628fba31be4a4ec1c4cf0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18373 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-28mem: Remove the ISA specialized versions of port proxy's read/write.Gabe Black
These selected their behavior based on ifdefs and had to be disabled when on the NULL ISA. The versions which take an explicit endianness have been renamed to just read/write instead of readGtoH and writeHtoG since the direction of the translation is obvious from context. Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18372 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-28mem: Minimize the use of MemObject.Gabe Black
MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed. Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-27python: Get rid of the VectorPort constructor.Gabe Black
The only thing it was doing beyond calling the parent Port __init__ was to set isVec, and nobody actually looks at that value later. Change-Id: I567cb583e6f02a6c18504b9bb20dd13b3c934822 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18175 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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