gem5 - gem5

Age	Commit message (Expand)	Author
2012-06-29	Bus: enable non/coherent buses sub-classes	Uri Wiener
2012-06-29	Mem: fix master id assertion in cache_impl.hh	Dam Sunwoo
2012-06-29	Mem: Fix a livelock resulting in LLSC/locked memory access implementation.	Matt Evans
2012-06-29	O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.	Nathanael Premillieu
2012-06-29	ARM: Fix identification of one RAS pop instruction.	Ali Saidi
2012-06-29	Cache: Only invalidate a line in the cache when an uncacheable write is seen.	Ali Saidi
2012-06-29	ARM: Update version of linux we claim to be to 3.0.0.	Ali Saidi
2012-06-29	ARM: Fix issue with predicted next pc being wrong because of advance() ordering.	Ali Saidi
2012-06-27	ARM: Fix address range issue with VExpress EMM	Ali Saidi
2012-06-11	ARM: implement the ProcessInfo methods	Anthony Gutierrez
2012-06-08	Timing CPU: Remove a redundant port pointer	Andreas Hansson
2012-06-08	Power: Fix MaxMiscDestRegs which was set to zero	Andreas Hansson
2012-06-07	X86 TLB: Add a missing = sign	Nilay Vaish
2012-06-07	mem: Delay deleting of incoming packets by one call.	Ali Saidi
2012-06-07	X86 TLB: Fix for gcc 4.4.3	Jayneel Gandhi
2012-06-05	cpu: Don't init simple and inorder CPUs if they are defered.	Anthony Gutierrez
2012-06-05	ISA: Back-out NoopMachInst as a StaticInstPtr change.	Ali Saidi
2012-06-05	cpt: update some comments in the checkpoint migration script	Ali Saidi
2012-06-05	stats: when applying an operation to two vectors sum the components first.	William Wang
2012-06-05	Mem: add per-master stats to physmem	Dam Sunwoo
2012-06-05	ARM: Add PCIe support to VExpress_EMM model and remove deprecated ELT	Geoffrey Blake
2012-06-05	ARM: removed extra white space	Chander Sudanthi
2012-06-05	ARM: Fix MPIDR and MIDR register implementation.	Chander Sudanthi
2012-06-05	ARM: PS2 encoding fix	Chander Sudanthi
2012-06-05	sim: Provide a framework for detecting out of data checkpoints and migrating ...	Ali Saidi
2012-06-05	stats: Add stats unittest for total calculations.	Ali Saidi
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-06-05	ARM: Fix over-eager assert in gic.	Ali Saidi
2012-06-05	stats: Provide a mechanism to get a callback when stats are dumped.	Mitchell Hayenga
2012-06-05	ARM: Fix compilation on ARM after Gabe's change.	Ali Saidi
2012-06-04	ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.	Gabe Black
2012-06-04	X86: Ensure that the CPUID instruction always writes its outputs.	Gabe Black
2012-06-04	X86: Ensure that the decoder's internal ExtMachInst is completely initialized.	Gabe Black
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-05-30	gcc: Small fixes to compile with gcc 4.7	Andreas Hansson
2012-05-30	Bus: Remove redundant packet parameter from isOccupied	Andreas Hansson
2012-05-30	Bus: Turn the PortId into a transport function parameter	Andreas Hansson
2012-05-30	Packet: Unify the use of PortID in packet and port	Andreas Hansson
2012-05-30	Packet: Updated comments for src and dest fields	Andreas Hansson
2012-05-30	Bridge: Split deferred request, response and sender state	Andreas Hansson
2012-05-28	X86: Use the HandyM5Reg to avoid a register read and some logic in the TLB.	Gabe Black
2012-05-27	X86: Move the GDT down to where it can be accessed in 32 bit mode.	Gabe Black
2012-05-27	X86: Truncate addresses to 32 bits except in 64 bit mode, not long mode.	Gabe Black
2012-05-26	ISA,CPU: Generalize and split out the components of the decode cache.	Gabe Black
2012-05-26	CPU: Merge the predecoder and decoder.	Gabe Black
2012-05-25	ISA: Make the decode function part of the ISA's decoder.	Gabe Black
2012-05-25	CPU: Simplify the implementation of the decode cache.	Gabe Black
2012-05-25	Decode: Make the Decoder class defined per ISA.	Gabe Black
2012-05-24	Cache: Remove dangling doWriteback declaration	Andreas Hansson