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AgeCommit message (Expand)Author
2014-02-23ruby: Simplify RubyPort flow control and routingAndreas Hansson
2014-02-23ruby: message buffer: refactor codeNilay Vaish
2014-02-23ruby: remove few not required #includesNilay Vaish
2014-02-23ruby: slicc: remove unused COPY_HEAD functionalityNilay Vaish
2014-02-23ruby: protocols: remove unused action z_stallNilay Vaish
2014-02-21ruby: network: move message buffers to base network class.Nilay Vaish
2014-02-21ruby: network: garnet: fixed: removes net_ptr from linksNilay Vaish
2014-02-21ruby: cache: remove not required variable m_cache_nameNilay Vaish
2014-02-20ruby: network: garnet: fixed: removes next cycle functionsNilay Vaish
2014-02-20ruby: controller: slight code refactoringNilay Vaish
2014-02-20ruby: mesi three level: rename incorrectly named filesNilay Vaish
2014-02-20ruby: network: removes unused code.Nilay Vaish
2014-02-20ruby: slicc: slight code refactoringNilay Vaish
2014-02-20ruby: message buffer: removes some unecessary functions.Nilay Vaish
2014-02-20kvm: Add support for multi-system simulationAndreas Sandberg
2014-02-18mem: Fix bug in PhysicalMemory use of mmap and munmapAndreas Hansson
2014-02-18dev: Include basic devices in NULL ISA buildAndreas Hansson
2014-02-18mem: Filter cache snoops based on address rangesAndreas Hansson
2014-02-18mem: Add a wrapped DRAMSim2 memory controllerAndreas Hansson
2014-02-18mem: Fix input to DPRINTF in CommMonitorAndreas Hansson
2014-02-09cpu: simple: Add support for using branch predictorsAndreas Sandberg
2014-02-06base: calls abort() from fatalNilay Vaish
2014-02-06ruby: memory controller: use MemoryNode *Nilay Vaish
2014-02-05x86: Fix x87 state transfer bugAndreas Sandberg
2014-02-02x86, kvm: Fix bug in the RFlags get and set functionsNikos Nikoleris
2014-01-30unittest: Fix build errorsOla Jeppsson
2014-01-29mem: Add additional tolerance to stride prefetcherMitch Hayenga
2014-01-29mem: Allowed tagged instruction prefetching in stride prefetcherMitch Hayenga
2014-01-29mem: prefetcher: add options, support for unaligned addressesMitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
2014-01-29cpu: fix bug when TrafficGen deschedules eventXiangyu Dong
2014-01-28arm: Enable umask syscall in SE modeMitch Hayenga
2014-01-28base: Fix race condition in the socket listen functionMitch Hayenga
2014-01-28mem: Remove redundant findVictim() input argumentAmin Farmahini
2014-01-28mem: Fixes a bug in simple_dram write mergingAmin Farmahini
2014-01-27x86: use lfpimm instead of limm for fptanNilay Vaish
2014-01-27x86: implements x87 add/sub instructionsNilay Vaish
2014-01-27x86: implements fxch instruction.Nilay Vaish
2014-01-27x86: correct error in emms instruction.Nilay Vaish
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2014-01-24arch: Make all register index flattening constAndreas Hansson
2014-01-24checker: CheckerCPU handling of MiscRegs was incorrectGeoffrey Blake
2014-01-24arch, cpu: Add support for flattening misc register indexes.Ali Saidi
2014-01-24cpu: Add support for Memory+Barrier instruction types in O3 cpu.Giacomo Gabrielli
2014-01-24cpu: Add support for instructions that zero cache lines.Ali Saidi
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2014-01-24mem: Add flag to request if it was generated by a page table walkGiacomo Gabrielli
2014-01-24mem: Add support for a security bit in the memory systemGiacomo Gabrielli
2014-01-24sim: Add openat/fstatat syscalls and fix mremapChris Adeniyi-Jones
2014-01-24mem: Remove explict cast from memhelper.Ali Saidi
2014-01-24Cache: Collect very basic stats on tag and data accessesTimothy M. Jones
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