gem5 - gem5

Age	Commit message (Expand)	Author
2017-09-26	sim: Don't add the NULL SimObject as a child of other SimObjects.	Gabe Black
2017-09-26	sim: Give the NullSimObject singleton a _name.	Gabe Black
2017-09-26	sim: Add a NullSimObject.descendants function.	Gabe Black
2017-09-26	sim: Add a clear_parent function to NullSimObject.	Gabe Black
2017-09-26	sim: Check the SimObjectVector.has_parent function to use the "any" function.	Gabe Black
2017-09-26	sim: Only consider non-NULL elements in SimObjectVector.has_parent.	Gabe Black
2017-09-26	sim: Add a set_parent to NullSimObject which does nothing.	Gabe Black
2017-09-25	mem: Fill the new packet ID fields with master IDs when tracing packets.	Gabe Black
2017-09-25	mem: Add a "map" of packet IDs to strings in probe traces.	Gabe Black
2017-09-25	mem: Trace the request master ID in the MemTraceProbe.	Gabe Black
2017-09-25	mem: Record the request master ID in the PacketInfo structure.	Gabe Black
2017-09-25	dev, virtio: Improvements to diod process handling	Anouk Van Laer
2017-09-21	alpha: Move some initialization logic from loadState into unserialize.	Gabe Black
2017-09-21	sim: Stop using loadState in the Root SimObject.	Gabe Black
2017-09-20	kvm: arm: Get rid of functions which just wrap the subclasses version.	Gabe Black
2017-09-11	stats: Move the swpipl function into the Alpha kernel stats.	Gabe Black
2017-09-11	stats: Get rid of some kernel stats related cruft.	Gabe Black
2017-09-06	cpu: Fix bi-mode branch predictor thresholds	Rico Amslinger
2017-09-01	cpu-minor: Fix for addr range coverage calculation	Pau Cabre
2017-08-30	arch-arm: Only increment SW PMU counters on writes to PMSWINC	Jose Marinho
2017-08-30	arch-arm: Add missing override keywords in fault.hh	Andreas Sandberg
2017-08-30	arch-x86: Add missing override in the X86 TLB	Andreas Sandberg
2017-08-30	arch-sparc: Add a FaultVals instantiation for VecDisabled	Andreas Sandberg
2017-08-30	arch-alpha: Add missing overrides	Andreas Sandberg
2017-08-30	python: Make GlobalExitEvent.getCode() return an int	Andreas Sandberg
2017-08-30	cpu-o3: fix data pkt initialization for split load	Matthias Hille
2017-08-28	x86: Use the new CondInst format for moves to/from control registers.	Gabe Black
2017-08-28	x86: Add a "CondInst" format for conditionally decoded instructions.	Gabe Black
2017-08-12	dev: Fix an IDE error check.	Gabe Black
2017-08-08	mem-cache: Delete squashed HWPrefetches	Pau Cabre
2017-08-02	base: Give more information when setting up asynchronous IO fails.	Gabe Black
2017-08-01	arch-arm: Use named constants for m5op instructions	Andreas Sandberg
2017-08-01	sim: Use named constants for pseudo ops	Andreas Sandberg
2017-08-01	kvm, arm: Switch to the device EQ when accessing ISA devices	Andreas Sandberg
2017-08-01	kvm: Add a helper method to access device event queues	Andreas Sandberg
2017-08-01	cpu, kvm: Fix deadlock issue when resuming a drained system	Andreas Sandberg
2017-08-01	arch-arm: Switch to DTOnly as the default machine type	Andreas Sandberg
2017-07-20	sim: Prevent segfault in the wakeCpu m5op if id is invalid	Jose Marinho
2017-07-19	cpu: Add missing rename of vector registers in the O3 CPU	Rekai Gonzalez-Alberquilla
2017-07-17	cpu,o3: Fixed checkpointing bug occuring in the o3 CPU	Anouk Van Laer
2017-07-17	sim, x86: Make clone a virtual function	Sean Wilson
2017-07-17	x86: Add stats to X86 TLB	Swapnil Haria
2017-07-17	riscv: Define register index constants using literals	Alec Roelke
2017-07-14	riscv: Disambiguate between the C and C++ versions of isnan and isinf.	Gabe Black
2017-07-14	riscv: Fix bugs with RISC-V decoder and detailed CPUs	Alec Roelke
2017-07-14	riscv: Add unused attribute to some registers.hh constants	Alec Roelke
2017-07-13	arch-arm: fix ldm of pc interswitching branch	Gedare Bloom
2017-07-12	ruby: Refactor some Event subclasses to lambdas	Sean Wilson
2017-07-12	arm: Refactor some Event subclasses to lambdas	Sean Wilson
2017-07-12	dev: Refactor some Event subclasses to lambdas	Sean Wilson