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AgeCommit message (Expand)Author
2012-10-15ruby banked array: do away with event schedulingNilay Vaish
2012-10-15ruby: reset timing after cache warm upNilay Vaish
2012-10-15Mem: Fix incorrect logic in bus blocksize checkAndreas Hansson
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Mem: Separate the host and guest views of memory backing storeAndreas Hansson
2012-10-15Checkpoint: Make system serialize call childrenAndreas Hansson
2012-10-15Mem: Use deque instead of list for bus retriesAndreas Hansson
2012-10-15Fix: Address a few minor issues identified by cppcheckAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Regression: Use CPU clock and 32-byte width for L1-L2 busAndreas Hansson
2012-10-15Clock: Inherit the clock from parent by defaultAndreas Hansson
2012-10-15Param: Fix proxy traversal to support chained proxiesAndreas Hansson
2012-10-15Mem: Use range operations in bus in preparation for stripingAndreas Hansson
2012-10-11Mem: Determine bus block size during initialisationAndreas Hansson
2012-10-11Doxygen: Update the version of the DoxyfileAndreas Hansson
2012-10-02ruby: makes some members non-staticNilay Vaish
2012-10-02ruby: changes to simple networkNilay Vaish
2012-10-02ruby: rename template_hack to templateNilay Vaish
2012-10-02ruby: remove unused code in protocolsNilay Vaish
2012-10-02ruby: remove some unused things in sliccNilay Vaish
2012-10-02ruby: move functional access to ruby systemNilay Vaish
2012-09-30MI coherence protocol: add copyright noticeNilay Vaish
2012-09-25MEM: Put memory system document into doxygenDjordje Kovacevic
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-25Statistics: Add a function to configure periodic stats dumpingSascha Bischoff
2012-09-25ARM: added support for flattened device tree blobsDam Sunwoo
2012-09-25O3: Pack the comm structures a bit better to reduce their size.Ali Saidi
2012-09-25mem: Add a gasket that allows memory ranges to be re-mapped.Ali Saidi
2012-09-25ARM: Squash outstanding walks when instructions are squashed.Ali Saidi
2012-09-25arm: Use a static_assert to test that miscRegName[] is completeAndreas Sandberg
2012-09-25base: Check for static_assert support and provide fallbackAndreas Sandberg
2012-09-25sim: Move CPU-specific methods from SimObject to the BaseCPU classAndreas Sandberg
2012-09-25sim: Remove SimObject::setMemoryModeAndreas Sandberg
2012-09-25CPU: Add abandoned instructions to O3 Pipe ViewerDjordje Kovacevic
2012-09-25ARM: Inst writing to cntrlReg registers not set as control instNathanael Premillieu
2012-09-25ARM: Predict target of more instructions that modify PC.Ali Saidi
2012-09-25build: Add missing dependencies when building param SWIG interfacesAndreas Sandberg
2012-09-23RubyPort and Sequencer: Fix drainingJoel Hestness
2012-09-21DRAM: Introduce SimpleDRAM to capture a high-level controllerAndreas Hansson
2012-09-21TrafficGen: Add a basic traffic generatorAndreas Hansson
2012-09-21Mem: Tidy up bus member variables typesAndreas Hansson
2012-09-21SE: Ignore FUTEX_PRIVATE_FLAG of sys_futexLluc Alvarez
2012-09-20bus: removed outdated warn regarding 64 B block sizesAnthony Gutierrez
2012-09-19Mem: Remove the file parameter from AbstractMemoryAndreas Hansson
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-09-19AddrRange: Simplify Range by removing stream input/outputAndreas Hansson
2012-09-19AddrRange: Remove unused range_multimapAndreas Hansson
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
2012-09-18ruby: eliminate typedef integer_tNilay Vaish
2012-09-18ruby: avoid using g_system_ptr for event schedulingNilay Vaish