Age | Commit message (Collapse) | Author |
|
src/arch/sparc/process.cc:
MachineBytes doesn't exist any more.
src/arch/sparc/regfile.cc:
Add in the miscRegFile for good measure.
src/cpu/o3/isa_specific.hh:
Add in a section for SPARC
src/cpu/o3/sparc/cpu.cc:
src/cpu/o3/sparc/cpu.hh:
src/cpu/o3/sparc/cpu_builder.cc:
src/cpu/o3/sparc/cpu_impl.hh:
src/cpu/o3/sparc/dyn_inst.cc:
src/cpu/o3/sparc/dyn_inst.hh:
src/cpu/o3/sparc/dyn_inst_impl.hh:
src/cpu/o3/sparc/impl.hh:
src/cpu/o3/sparc/params.hh:
src/cpu/o3/sparc/thread_context.cc:
src/cpu/o3/sparc/thread_context.hh:
Sparc version of this file.
--HG--
extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
|
|
into ewok.(none):/home/gblack/m5/newmemo3
--HG--
extra : convert_revision : e8d6ce19a83fe526112c1dd61c48196eb8c0951f
|
|
into zower.eecs.umich.edu:/eecshome/m5/newmem
--HG--
extra : convert_revision : 7dbd30ce5579dd62d5f54bb5d75cf12346bc5d1d
|
|
--HG--
extra : convert_revision : 57ea1e1d3b75e35abb3310d392ec70086fff699a
|
|
--HG--
extra : convert_revision : 7372b7a92b3c9d05388acb43ba58ada18464fa24
|
|
--HG--
extra : convert_revision : 89be55bd3f4f9b452a680a98b69ce42b80546769
|
|
--HG--
extra : convert_revision : 383b72c130b20f3d7cde4e08fa36a481f3c0bf7c
|
|
--HG--
extra : convert_revision : f93182ed41057025cc10df443b24e82fbe783df6
|
|
src/arch/sparc/isa/base.isa:
Fix a constant.
src/arch/sparc/isa/decoder.isa:
Made carry calculation more consistent.
src/arch/sparc/isa/operands.isa:
Use the right constant.
--HG--
extra : convert_revision : 25b3a09ff20d4b8e1a95ee8a983d14ef3cfe73bb
|
|
--HG--
extra : convert_revision : 378b2d9791e6282539900a2261ad2275d726b4be
|
|
we can make our own hypervisor binary, we probably won't need it.
--HG--
extra : convert_revision : 168883e4a5d3760962cd9759a6f41c66f5a6402a
|
|
L2's in FS
Fix a small writeback bug when missing in the L2 in atomic mode
src/mem/bus.cc:
Fix a comment to make sense
src/mem/cache/cache_impl.hh:
Do a functional access to levels above on a read as a temporary solution for L2's in FS
Also fix a small writeback miss in L2 issue
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Do a functional access to levels above on a read as a temporary solution for L2's in FS
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
Update ref's for writeback changes
--HG--
extra : convert_revision : 937febd577b16b7fd97a5a68acaf53541828a251
|
|
into zower.eecs.umich.edu:/eecshome/m5/newmem
--HG--
extra : convert_revision : 75f3398e38e18eb1f8248e23708d7a8d8cce0fc5
|
|
--HG--
extra : convert_revision : 71cf02edffbc7029666c0d9c97b67e1d32332758
|
|
formatting functions.
--HG--
extra : convert_revision : e3aa5919a6480aa01924c832a86fa1e8ddf5ba0d
|
|
--HG--
extra : convert_revision : 8707bbed2aeb80613f86503e92b63853767adaa9
|
|
manual of what happens during a trap says it should be 0, and other places say it doesn't matter.
--HG--
extra : convert_revision : 9ecb6af06657e936a208cbeb8e4a18305869b949
|
|
description.
--HG--
extra : convert_revision : a49de5fcfbea307c971964b8a68b95eb5d9a2bf4
|
|
--HG--
extra : convert_revision : 2dd830c6b3b5df894608b7596250b0181a3dfdf0
|
|
src/cpu/o3/alpha/cpu_impl.hh:
Handle the PhysicalPort and VirtualPort in the ThreadState.
src/cpu/o3/cpu.cc:
Initialize the thread context.
src/cpu/o3/thread_context.hh:
Add new function to initialize thread context.
src/cpu/o3/thread_context_impl.hh:
Use code now put into function.
src/cpu/simple_thread.cc:
Move code to ThreadState and use the new helper function.
src/cpu/simple_thread.hh:
Remove init() in this derived class; use init() from ThreadState base class.
src/cpu/thread_state.cc:
Move setting up of Physical and Virtual ports here. Change getMemFuncPort() to connectToMemFunc(), which connects a port to a functional port of the memory object below the CPU.
src/cpu/thread_state.hh:
Update functions.
--HG--
extra : convert_revision : ff254715ef0b259dc80d08f13543b63e4024ca8d
|
|
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : 1fc55d7d5707bb7c63790aab306ca5ea8ade5fab
|
|
[phys,virt]Port correctly
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Call the thread context initialization
--HG--
extra : convert_revision : d7dc2a8b893dc670077b7f6150d4b710a1778620
|
|
only once.
--HG--
extra : convert_revision : b64bb495c1bd0c4beb3db6ca28fad5af4d05ef8e
|
|
--HG--
extra : convert_revision : bc12b3b2e9ee02f42c437cbc20680ea00e19a801
|
|
--HG--
extra : convert_revision : a2d3cf29ab65c61af27d82a8c421a41a19fd5aeb
|
|
into zower.eecs.umich.edu:/eecshome/m5/newmem
--HG--
extra : convert_revision : 74b2352b8f088e38cd1ecf3a8233b45df0476d93
|
|
into zower.eecs.umich.edu:/home/gblack/m5/newmemmemops
--HG--
extra : convert_revision : c49b760eac758dbde30867cb638fcb3b790f4721
|
|
configs/common/FSConfig.py:
Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
Create a T1000 platform
src/arch/sparc/miscregfile.cc:
Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
Truncate an ExtMachInst to a MachInst before comparing with Legion.
--HG--
extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
|
|
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : 8d61b474428d494b1a5382e4cf95934ad54e35dd
|
|
src/cpu/simple/timing.cc:
Various updates for deleting requests more properly.
The major change is moving the deletion of the fetch request/packet to after the instruction has executed and completed. This should fix a few bugs because Ron's memory system didn't expect a call for a functional access while a timing access was being processed.
--HG--
extra : convert_revision : c7cf114bb1ff3cdaa7b0a40ed4c5302dc9d3a522
|
|
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : b216fcdb2632dce68ac18932b0c13408eb1aeaf4
|
|
src/mem/bus.cc:
Make it so that invalidates being sent from the responder up don't call the responder
but they should also not Panic.
src/mem/packet.hh:
If we don't have data in the packet, don't call deleteData:
Example: InvalidateRequests never have data.
--HG--
extra : convert_revision : 18766bc9f3bb4d852ac651d094254d347abd1634
|
|
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
--HG--
extra : convert_revision : 966246877ac1f1e6c2675d413b0b405cccfecbeb
|
|
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
--HG--
extra : convert_revision : 8e805b9bbd5c64c2e5951384b3c6ef712062d08c
|
|
--HG--
extra : convert_revision : 7e27b23b66c743b4625a1dd9d8d6ba61bff45168
|
|
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision : 6abd919711966eaaa157483557a3f953b02dde01
|
|
make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build
src/arch/sparc/interrupts.hh:
make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build
--HG--
extra : convert_revision : 5f469d0cf897479b42703104cd801a8ef923fcae
|
|
--HG--
extra : convert_revision : 5b0a977a162a1b881b97a3185fb386cc76632a4a
|
|
--HG--
extra : convert_revision : 566d73438efb87ca683e4dee23454d880db3dfc7
|
|
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
--HG--
extra : convert_revision : cda58e6e63f2f909b85a510fb76d35d49d8042b9
|
|
--HG--
extra : convert_revision : 0be66513cb0cff07c0c2b50c97c1ea74d52b0dc9
|
|
--HG--
extra : convert_revision : 4504f08fd94792819bd4419bbd2e0ebd1d7f29e9
|
|
--HG--
extra : convert_revision : 7bdf68f445b79b1b5dbcdfa5fa1005c68d03724c
|
|
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
--HG--
extra : convert_revision : 753831a9f6f79d07e6ee122ab894e24161d2e722
|
|
--HG--
extra : convert_revision : cd2eb8c00adcb34b8693a4d1a66187927c0f6803
|
|
src/mem/bridge.cc:
Update brdiges, now that snoop addresses are properly forwarded.
Bus bridge should only handle snoops on the second phase (SNOOP_COMMIT)
src/mem/bus.cc:
src/mem/bus.hh:
Make sure if a busBridge has access to both things that snoop and things that respond it only takes the request once
--HG--
extra : convert_revision : 26cc9ee4429be45d4476fa435e0e9a54843c2509
|
|
--HG--
extra : convert_revision : 7f082ba5c1cd2445aec731950c31a877aac23a75
|
|
sendTiming has not returned in the call stack.
src/mem/cache/base_cache.cc:
Sometimes a functional access comes while waiting on a outstanding packet being sent.
This could be because Timing CPU does some post processing on the recvTiming which send functional access.
Either the CPU should leave the pkt/req around (so They can be referenced in the mem system). Or the mem
system should remove them from outstanding lists and reinsert them if they fail in the sendTiming.
I did the later, eventually we should consider doing the former if that is the correct behavior.
--HG--
extra : convert_revision : be41e0d2632369dca9d7c15e96e5576d7583fe6a
|
|
--HG--
extra : convert_revision : 736372131b046eccf3520292fb3c086dc568d918
|
|
src/mem/bus.cc:
Only call snoop once per port, need to fix it so snoop ranges that overlap aren't added to list
Functional accesses that call snoop and it goes to a higher bus may change the src, reset it after each snoop.
--HG--
extra : convert_revision : 7276059c798a85cb9d138ccc5531298ecd055c13
|