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AgeCommit message (Expand)Author
2009-11-18ruby: fixed dma mi example to work with multiple dma portsBrad Beckmann
2009-11-18m5: removed master and slave deletions.Brad Beckmann
2009-11-18m5: fixed destructor to deschedule the tickEvent and eventBrad Beckmann
2009-11-18ruby: getPort function fixBrad Beckmann
2009-11-18ruby: Fixed Directory memory destructorBrad Beckmann
2009-11-18m5: Added isValidSrc and isValidDest calls to packet.hhBrad Beckmann
2009-11-18ruby: included ruby config parameter ports per coreBrad Beckmann
2009-11-18ruby: Added error check for openning the ruby config fileBrad Beckmann
2009-11-18ruby: Support for merging ALPHA_FS and rubyBrad Beckmann
2009-11-18ruby: Added more info to bridge error messageBrad Beckmann
2009-11-18ruby: Ruby 64-bit address output fixes.Brad Beckmann
2009-11-18ruby: Ruby destruction fix.Brad Beckmann
2009-11-18ruby: Ruby debug print fixes.Brad Beckmann
2009-11-17ARM: Begin implementing CP15Ali Saidi
2009-11-17ARM: Differentiate between LDM exception return and LDM user regs.Ali Saidi
2009-11-17ARM: Boilerplate full-system code.Ali Saidi
2009-11-16imported patch isa_fixes2.diffAli Saidi
2009-11-15ARM: Make the exception return form of ldm restore CPSR.Gabe Black
2009-11-15ARM: Create a new type of load uop that restores spsr into cpsr.Gabe Black
2009-11-14ARM: Check in the actual change from the last commit.Gabe Black
2009-11-14ARM: Fix up the implmentation of the msr instruction.Gabe Black
2009-11-14ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.Gabe Black
2009-11-14ARM: Add a bitfield to indicate if an immediate should be used.Gabe Black
2009-11-14ARM: Write some functions to write to the CPSR and SPSR for instructions.Gabe Black
2009-11-14ARM: Fix up the implmentation of the mrs instruction.Gabe Black
2009-11-14ARM: More accurately describe the effects of using the control operands.Gabe Black
2009-11-14ARM: Hook up the moded versions of the SPSR.Gabe Black
2009-11-14SE: Fix SE mode OS X compilation.Ali Saidi
2009-11-14ARM: Move around decoder to properly decode CP15Ali Saidi
2009-11-11X86: add ULL to 1's being shifted in 64-bit valuesVince Weaver
2009-11-10ARM: Fix some bugs in the ISA desc and fill out some instructions.Gabe Black
2009-11-10Merge with the head.Gabe Black
2009-11-10Mem: Eliminate the NO_FAULT request flag.Gabe Black
2009-11-10ARM: Implement fault classes.Gabe Black
2009-11-10ARM: Fix the integer register indexes.Gabe Black
2009-11-10X86: Fix bugs in movd implementation.Vince Weaver
2009-11-10X86: Remove double-cast in Cvtf2i micro-opVince Weaver
2009-11-09syscall: missing initializer in getcwd callVince Weaver
2009-11-08X86: Don't panic on faults on prefetches in SE mode.Gabe Black
2009-11-08X86: Explain what really didn't work with unmapped addresses in SE mode.Gabe Black
2009-11-08X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE.Gabe Black
2009-11-08automergeNathan Binkert
2009-11-08scons: deal with generated .py files properlySteve Reinhardt
2009-11-08ARM: Support forcing load/store multiple to use user registers.Gabe Black
2009-11-08ARM: Simplify the load/store multiple generation code.Gabe Black
2009-11-08compile: wrap 64bit numbers with ULL() so 32bit compiles workNathan Binkert
2009-11-08ARM: Split the condition codes out of the CPSR.Gabe Black
2009-11-08ARM: Add in more bits for the mon mode.Gabe Black
2009-11-08ARM: Get rid of NumInternalProcRegs.Gabe Black
2009-11-08ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.Gabe Black
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