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AgeCommit message (Expand)Author
2011-03-17Automated merge with ssh://hg@repo.m5sim.org/m5Ali Saidi
2011-03-17ARM: Add minimal ARM_SE support for m5threads.Chris Emmons
2011-03-17ARM: Fix subtle bug in LDM.Ali Saidi
2011-03-17ARM: Implement the Instruction Set Attribute Registers (ISAR).Ali Saidi
2011-03-17ARM: Identify branches as conditional or unconditional and direct or indirect.Ali Saidi
2011-03-17ARM: Fix small bug with VLDM/VSTM instructions.Ali Saidi
2011-03-17ARM: Detect and skip udelay() functions in linux kernel.Ali Saidi
2011-03-17ARM: Allow conditional quiesce instructions.Ali Saidi
2011-03-17ARM: Fix RFE macrop.Matt Horsnell
2011-03-17ARM: Rename registers used as temporary state by microops.Matt Horsnell
2011-03-17O3: Send instruction back to fetch on squash to seed predecoder correctly.Ali Saidi
2011-03-17O3: Cleanup the commitInfo comm struct.Ali Saidi
2011-03-17ARM: Previous change didn't end up setting instFlags, this does.Ali Saidi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-03-17O3: Fix unaligned stores when cache blockedAli Saidi
2011-03-17Ruby: minor bugfix, line did not adhere to some macro usage conventions.Lisa Hsu
2011-03-17Ruby: expose a simple mod function in slicc interface.Lisa Hsu
2011-03-11SCons: Stop embedding the mercurial revision into the binary.Gabe Black
2011-03-11Gems: Eliminate the now unused GEMS_ROOT scons variable.Gabe Black
2011-03-11Ruby: Get rid of the dead ruby tester.Gabe Black
2011-03-08Alpha: Fix the datatypes of some values read from the simulated kernel.Yi Xiang
2011-03-03SCons: Clean up some inconsistent capitalization in scons options.Gabe Black
2011-03-02X86: Use the npc as the pc when doing a nativetrace, not what M5 considers th...Gabe Black
2011-03-02X86: Decode the mysterious and elusive ffreep x87 instruction.Gabe Black
2011-03-01Spelling: Fix the a spelling error by changing mmaped to mmapped.Gabe Black
2011-03-01X86: Mark IO reads and writes as non-speculative.Gabe Black
2011-03-01X86: Mark prefetches as such in their instruction and request flags.Gabe Black
2011-03-01Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBufferNilay Vaish
2011-03-01Ruby: Mention that Ruby's bound checking option only applies to Ruby.Gabe Black
2011-02-27X86: If PCI config space is disabled, pass through to regular IO addresses.Gabe Black
2011-02-27X86: Use regular read requests in the walker instead of read exclusive.Gabe Black
2011-02-26getopt: Remove GPL code.Nathan Binkert
2011-02-25Ruby: Remove store bufferNilay Vaish
2011-02-25Ruby: Remove librubyNilay Vaish
2011-02-25Ruby: Make Address.hh independent of RubySystemNilay Vaish
2011-02-25Ruby: Make DataBlock.hh independent of RubySystemNilay Vaish
2011-02-25O3CPU: Fix iqCount and lsqCount SMT fetch policies.Timothy M. Jones
2011-02-23ruby: automate permission settingBrad Beckmann
2011-02-23MOESI_hammer: cache probe address clean upBrad Beckmann
2011-02-23ruby: cleaned up access permission enumBrad Beckmann
2011-02-23ruby: removed unsupported protocol filesBrad Beckmann
2011-02-23inorder: InstSeqNum bugKorey Sewell
2011-02-23inorder: dyn inst initializationKorey Sewell
2011-02-23inorder: cache packet handlingKorey Sewell
2011-02-23Mem: Print out memory when access > 8 bytesAli Saidi
2011-02-23ARM: Set ITSTATE correctly after FlushPipeAli Saidi
2011-02-23ARM: This panic can be hit during misspeculation so it can't exist.Ali Saidi
2011-02-23ARM: Bad interworking warn way to noisy when running real code w/misspeculation.Ali Saidi
2011-02-23O3: When a prefetch causes a fault, don't record it in the instAli Saidi
2011-02-23ARM: NEON instruction templates modified to set the predicate flag to false w...Giacomo Gabrielli