Age | Commit message (Collapse) | Author |
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro
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extra : convert_revision : 757e1d79033e6f8e0aaaf5ecaf14077d416cff8e
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-o3-spec
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extra : convert_revision : 12f10c174f0eca1ddf74b672414fbe78251f686b
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
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extra : convert_revision : 05f738ab6cf1e8bd2940f4ce20602f1e8ad1af48
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src/cpu/o3/cpu.cc:
Use proper cycles for these equations.
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extra : convert_revision : 4f393a5471656b29cecbacfcb337992239775915
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renamed part and a control part for the different bitfields, but the renamed part is all that's actually used.
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not a cpp file because c99
(which defines fenv) doesn't necessarily extend to c++ and it is a problem with solaris. If really
desired this could wrap the ieeefp interface found in bsd* as well, but I see no need at the moment.
src/arch/alpha/isa/fp.isa:
src/arch/sparc/isa/formats/basic.isa:
use m5_fesetround()/m5_fegetround() istead of fenv interface directly
src/arch/sparc/isa/includes.isa:
use base/fenv instead of fenv directly
src/base/SConscript:
add fenv to sconscript
src/base/fenv.hh:
src/base/random.cc:
m5 implementation to standerdize fenv across platforms.
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extra : convert_revision : 38d2629affd964dcd1a5ab0db4ac3cb21438e72c
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-o3-spec
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extra : convert_revision : 26118d0dce464405148d2693fee4561fa0ce10ff
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encumbered directory
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they're used
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extra : convert_revision : ed5351f291d45d585bf811a062e162e16b86e886
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-o3-spec
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extra : convert_revision : d18cce378fe3390c6e708945b9ea7c76c2d20a81
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checked for control flow because we can pull out microops until we run out of buffer. This prevents microops from being interpretted as branches because the pc doesn't become npc.
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extra : convert_revision : 9fff7c6c32900692bbc567ecb75701c9c73da259
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extra : convert_revision : 26ea87bfe9e5c27134eb9a15bf9e4629afae6c69
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handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
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extra : convert_revision : 8b9c603616bcad254417a7a3fa3edfb4c8728719
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Oops!
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this as well.
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extra : convert_revision : edd3f9a83cc2722b6e0eff0eff4a8e034b0f6ec6
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squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect.
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extra : convert_revision : b42c4eb28b4fbba66c65cbd0a5033bf886c1532d
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and python code into m5 to allow swig an python code to
easily added by any SConscript instead of just the one in
src/python. This provides SwigSource and PySource for
adding new files to m5 (similar to Source for C++). Also
provides SimObject for including files that contain SimObject
information and build the m5.objects __init__.py file.
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extra : convert_revision : 38b50a0629846ef451ed02f96fe3633947df23eb
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or automatically do Split(). It isn't used anywhere, and
isn't very consistent with the python features that are
about to be added. Do accept SCons.Node.FS.File arguments
though.
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extra : convert_revision : 0f3bb0e9e6806490330eea59a104013042b4dd49
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unproxy() needs to return a new object otherwise all
instances will use the same value. This fix is more
or less unique to NextEthernetAddr because its use of
the proxy stuff is a bit different than everything else.
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extra : convert_revision : 2ce452e37d00b9ba76b6abfaec0ad2e0073920d7
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to be created
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extra : convert_revision : 826cc692614528f987c80c3410cb025190f0a4e0
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
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extra : convert_revision : 50102b96ba07b2b132d649a111268ee1f08c2147
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implementations from using doubles to using concatenated singles.
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extra : convert_revision : 609ba35bbb13cbd1998e93957cb051461442d1f9
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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extra : convert_revision : c5275ef3e53393496a2ebe05b2f516884bb392f9
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test the stub code for instructions.
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extra : convert_revision : a377daf20545dfcbb0f97d8cafbe3d68416dc4b2
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parser as a unit.
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extra : convert_revision : eec4b188b44b80cee643542bbd1aaa139cbc4ef0
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unimplemented instructions in their microcode. This is useful if certain variations of an instruction are implemented, but, for instance, it's memory based versions aren't.
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
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extra : convert_revision : a250eed999be9b8acd6f420fdfe8f1b02905beb1
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extra : convert_revision : a1a218d3294515184689041487057495223360b7
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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extra : convert_revision : 1396ed5b264d29377ef9793a763225a93181f65f
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extra : convert_revision : 1ffe0c497e10fef1eb84b3c97c00b98d820fbb97
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size than the architected one. Also fixed some asserts.
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extra : convert_revision : 26e7863919d1b976ba8cad747af475a6f18e9440
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
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extra : convert_revision : dba3542ab73cc8ae46347a14ae4c133f1276011c
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IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.
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extra : convert_revision : cfd32808592832d7b6fbdaace5ae7b17c8a246e9
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and added some comments to main.isa
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extra : convert_revision : 1534ae7d5a9e95bf662d79a04f9286c227541c6c
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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extra : convert_revision : 8e624bb95cb9f478ca7ac1dbbd64e20674e3e224
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x86-centric stuff.
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extra : convert_revision : 5e7e8026e24ce44a3dac4a358e0c3e5560685958
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seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere.
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rename : src/arch/x86/isa/formats/macroop.isa => src/arch/x86/isa/macroop.isa
extra : convert_revision : 5ab40eedf574fce438d9fe90e00a496dc95c8bcf
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sizes, and sign extend the 32-bit-acting-like-64-bit-immediates.
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extra : convert_revision : e59b747198cc79d50045bd2dc45b2e2b97bbffcc
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
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extra : convert_revision : b7e89d32df946ea24c438292308f5fc8248f8bd9
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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extra : convert_revision : efdbf9787383dc1df544b7276f8120285e69bf69
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