gem5 - gem5

Age	Commit message (Expand)	Author
2011-05-13	ARM: Construct the predicate test register for more instruction programatically.	Ali Saidi
2011-05-13	ARM: Further break up condition code into NZ, C, V bits.	Ali Saidi
2011-05-13	ARM: Remove the saturating (Q) condition code from the renamed register.	Ali Saidi
2011-05-13	ARM: Break up condition codes into normal flags, saturation, and simd.	Ali Saidi
2011-05-13	Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.	Chander Sudanthi
2011-05-13	ARM: Better RealView/Versatile EB platform support.	Chander Sudanthi
2011-05-13	O3: Fix an issue with a load & branch instruction and mem dep squashing	Geoffrey Blake
2011-05-12	stats: delete mysql support	Nathan Binkert
2011-05-12	stats: move code that loops over all stats into python	Nathan Binkert
2011-05-12	stats: better expose statistics to python.	Nathan Binkert
2011-05-09	work around gcc 4.5 warning	Nathan Binkert
2011-05-07	NetworkTest: added sim_cycles parameter to the network tester.	Tushar Krishna
2011-05-07	network: added Torus and Pt2Pt topologies	Tushar Krishna
2011-05-07	Trace: Remove the options trace-help and trace-flags	Nilay Vaish
2011-05-06	X86: Fix the Lldt instructions so they load the ldtr and not the tr.	Gabe Black
2011-05-05	ruby: use RubyMemory flag & remove setDebug() functionality	Korey Sewell
2011-05-04	ARM: Add support for loading the a bootloader and configuring parameters for it	Ali Saidi
2011-05-04	ARM: Implement WFE/WFI/SEV semantics.	Prakash Ramrakhyani
2011-05-04	ARM: Add support for MP misc regs and broadcast flushes.	Ali Saidi
2011-05-04	ARM: Make GIC handle IPIs and multiple processors.	Prakash Ramrakhyani
2011-05-04	ARM: Add snoop control unit device.	Ali Saidi
2011-05-04	ARM: Add support for some more registers in the real view controller.	Ali Saidi
2011-05-04	Debug: Add a function to cause the simulator to create a checkpoint from GDB.	Ali Saidi
2011-05-04	CPU: Add some useful debug message to the timing simple cpu.	Ali Saidi
2011-05-04	CPU: Fix a case where timing simple cpu faults can nest.	Ali Saidi
2011-05-04	O3: Remove assertion for case that is actually handled in code.	Ali Saidi
2011-05-04	Core: Add some documentation about the sim clocks.	Ali Saidi
2011-05-04	RealView: Fix the 24 and 100MHz clocks which were providing incorrect values.	Chris Emmons
2011-05-04	O3: Fix a small corner case with the lsq hazard detection logic.	Ali Saidi
2011-05-04	ARM: Add vfpv3 support to native trace.	Ali Saidi
2011-05-04	ARM: Fix small bug with vcvt instruction	Ali Saidi
2011-05-04	debug: fix help output	Nathan Binkert
2011-05-02	ruby: dbg: use system ticks instead of cycles	Korey Sewell
2011-04-28	network: set the ExtLink bw to 16 bytes	Brad Beckmann
2011-04-28	garnet: removed flit_width from Routers	Brad Beckmann
2011-04-28	network: adjusted default endpoint bandwidth	Brad Beckmann
2011-04-28	network: removed the unused network-wide latency param	Brad Beckmann
2011-04-28	network: moved network config params	Brad Beckmann
2011-04-28	network: basic link bw for garnet and simple networks	Brad Beckmann
2011-04-28	network: convert links & switches to first class C++ SimObjects	Brad Beckmann
2011-04-28	garnet: cleaned up flexible network header file	Brad Beckmann
2011-04-28	ruby: moved topology to the top network directory	Brad Beckmann
2011-04-28	ruby: removed dated comment in SimpleNetwork	Brad Beckmann
2011-04-28	event: fix PythonEvent	Nathan Binkert
2011-04-25	base: include types.hh in base/stats/mysql.hh	Nilay Vaish
2011-04-23	X86: When decoding a memory only inst, fault on reg encodings, don't assert.	Gabe Black
2011-04-20	stats: ensure that stat names are valid	Nathan Binkert
2011-04-20	stats: one more name violation	Nathan Binkert
2011-04-20	fix some build problems from prior changesets	Nathan Binkert
2011-04-20	stats: add user settable separator string for arrayed stats	Brad Danofsky