summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2014-08-10config: Add SubSystem container for simobjectsGeoffrey Blake
2014-08-10config: Add hooks to enable new config sysGeoffrey Blake
2014-08-10cpu: Ensure the traffic generator suppresses non-memory packetsAndreas Hansson
2014-08-10base: Remove unused filesAndreas Hansson
2014-07-28mem: refactor LRU cache tags and add random replacement tagsAnthony Gutierrez
2014-07-23cpu: `Minor' in-order CPU modelAndrew Bardsley
2014-07-19syscall emulation: fix fast build issueSteve Reinhardt
2014-07-18x86: make PioBus return BadAddress errorsBinh Pham
2014-07-18sim: remove unused MemoryModeStrings arraySteve Reinhardt
2014-07-18kern: get rid of unused linux syscall filesSteve Reinhardt
2014-07-18syscall emulation: fix DPRINTF arg ordering bugSteve Reinhardt
2014-07-09base: fix operator== for comparing EthAddr objectsAnthony Gutierrez
2014-07-02base: fix some bugs in EthAddrAnthony Gutierrez
2014-07-01util: Add DVFS perfLevel to checkpoint upgrade scriptRadhika Jagtap
2014-06-30power: Add basic DVFS support for gem5Stephan Diestelhorst
2014-06-30mem: DRAMPower trace outputAndreas Hansson
2014-06-30mem: Add bank and rank indices as fields to the DRAM bankAndreas Hansson
2014-06-30mem: Extend DRAM row bits from 16 to 32 for larger densitiesAndreas Hansson
2014-06-30cpu: implement a bi-mode branch predictorAnthony Gutierrez
2014-06-21x86: fix table walker assertionBinh Pham
2014-06-21o3: make dispatch LSQ full check more selectiveBinh Pham
2014-06-21o3: split load & store queue full cases in renameBinh Pham
2014-06-10scons: Bump the compiler version to gcc 4.6 and clang 3.0Andreas Hansson
2014-06-09sim: More rigorous clocking commentsJoel Hestness
2014-05-31style: eliminate equality tests with true and falseSteve Reinhardt
2014-05-23ruby: slicc: remove unused ids DNUCA*Nilay Vaish
2014-05-23ruby: remove old protocol documentationNilay Vaish
2014-05-23ruby: message buffer: drop dequeue_getDelayCycles()Nilay Vaish
2014-05-23cpu: o3: remove stat totalCommittedInstsNilay Vaish
2014-05-12syscall emulation: clean up & comment SyscallReturnSteve Reinhardt
2014-05-09mem: Update DDR3 and DDR4 based on datasheetsAndreas Hansson
2014-05-09mem: Add DRAM cycle timeAndreas Hansson
2014-05-09mem: Simplify DRAM response schedulingAndreas Hansson
2014-05-09mem: Add precharge all (PREA) to the DRAM controllerAndreas Hansson
2014-05-09mem: Remove printing of DRAM paramsAndreas Hansson
2014-05-09mem: Add tRTP to the DRAM controllerAndreas Hansson
2014-05-09mem: Merge DRAM latency calculation and bank state updateAndreas Hansson
2014-05-09mem: Add tWR to DRAM activate and precharge constraintsAndreas Hansson
2014-05-09mem: Merge DRAM page-management calculationsAndreas Hansson
2014-05-09mem: Add DRAM power states to the controllerAndreas Hansson
2014-05-09mem: Ensure DRAM refresh respects timingsAndreas Hansson
2014-05-09mem: Make DRAM read/write switching less conservativeAndreas Hansson
2014-04-17arm: Make sure UndefinedInstructions are properly initializedAli Saidi
2014-04-17arm: allow DC instructions by default so SE mode worksAli Saidi
2014-04-17sim, arm: implement more of the at variety syscallsAli Saidi
2014-05-09cpu: Useful getters for ActivityRecorderAndrew Bardsley
2014-05-09cpu: Add flag name printing to StaticInstAndrew Bardsley
2014-05-09cpu: Timebuf const accessorsAndrew Bardsley
2014-05-09arm: Add branch flags onto macroopsAndrew Bardsley
2014-05-09cpu: Allow setWhen on trace objectsAndrew Bardsley
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-29 03:16:34 +0000