| Age | Commit message (Collapse) | Author |
|---|
|
These settings are invariant, so there's no reason to apply them over
and over again for the child environments used for various build
products.
Change-Id: Icb4053105e4f1c43008f2422ba30c7206b7ff365
Reviewed-on: https://gem5-review.googlesource.com/5981
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
This function doesn't seem to be used by anything. A similar one off
mechanism exists for SimObjects which is we might also be able to get
rid of.
Change-Id: I65038c3495fa69cf94042dc78f09876d5e9a557f
Reviewed-on: https://gem5-review.googlesource.com/5841
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
|
|
Tags are just arbitrary strings which are attached to source files
which mark them as having some property. By default, all source files
have the "gem5 lib" tag added to them which marks them as part of the
gem5 library, the primary component of the gem5 binary but also a
seperable component for use in, for example, system C.
The tags can be completely overridden by setting the "tags" parameter
on Source, etc., functions, and can be augmented by setting "add_tags"
which are tags that will be added, or alternatively additional tags.
It's possible to specify both, in which case the tags will be set to
the union of tags and add_tags. add_tags is supposed to be a way to
add extra tags to the default without actually overriding the default.
Both tags and add_tags can be a list/tuple/etc of tags, or a single
string which will be converted into a set internally.
Other existing tags include:
1. "python" for files that need or are used with python and are
excluded when the --without-python option is set
2. "main" for the file(s) which implement the gem5 binary's main
function.
3. The name of a unit test to group its files together.
4. Tags which group source files for partial linking.
By grouping the "tags" into a single parameter instead of taking all
extra parameters as tags, the extra parameters can, in the future, be
passed to the underlying scons environment. Also, the tags are either
present or not. With guards, they could be present and True, present
and False, or not present at all.
Change-Id: I6d0404211a393968df66f7eddfe019897b6573a2
Reviewed-on: https://gem5-review.googlesource.com/5822
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Delete the current version of foo.ini which was modified, restore the
previous version, and initest.ini. Preprocess initest.ini which
includes foo.ini, and tidy up the resulting file. This file will
(mostly) get the initest unit test to work. Some other cleanups are
still necessary.
Change-Id: I4e46abc73ac89f88177eec92f572452f63ba8019
Reviewed-on: https://gem5-review.googlesource.com/6041
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
|
|
This has been broken since February. The interface for opening
initializing where the stats output should go was changed, but the
test wasn't updated.
Change-Id: I54bd8be15bf870352d5fcfad95ded28d87c7cc5a
Reviewed-on: https://gem5-review.googlesource.com/6001
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Add support for software breakpoints as signalled by the aarch64 brk
instruction. This introduces a new SoftwareBreakpoint fault.
Change-Id: I93646c3298e09d7f7b0983108ba8937c7331297a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5721
Reviewed-by: Giacomo Gabrielli <Giacomo.Gabrielli@arm.com>
|
|
Since EL2 is not available in secure mode, any HVC call from secure mode
should be treated as undefined. This behaviour was implemented in
aarch32 HVC but not in 64 bit version
Change-Id: Ibaa4d8b1e8fe01d2ba3ef07494c09a4d3e7e87b0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5921
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
This patch adds all system calls present in riscv-gnu-toolchain at
commit hash 65cb174. Many of them do not have implementations in gem5, so
they are just placeholders.
[Remove the variadic macro and replace it with a function that has
default arguments because variadic macros may not be portable across
compilers]
[Remove spaces around default arguments of createSyscall for better
style]
[Switch from using a loose function to using SyscallDesc's new
constructor]
Change-Id: Iff97c689109121b39df423c72d0e79c6366e31b9
Reviewed-on: https://gem5-review.googlesource.com/5322
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
|
|
This patch adds a default value of unimplementedFunc to SyscallDesc's
constructor's second argument, which makes adding system call
placeholders to SE mode cleaner.
Change-Id: I3e7efb3a887cc52d16d2095d3dd2e2a96fb882fb
Reviewed-on: https://gem5-review.googlesource.com/5501
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
|
|
Change-Id: I24008c1e2a94ad8dc4cc13739214928eb846a496
Reviewed-on: https://gem5-review.googlesource.com/5483
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
|
|
Change-Id: Ifbeee464e2d7f872e192f065ad3494f52d274596
Reviewed-on: https://gem5-review.googlesource.com/5482
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
|
|
These were just raw C++ classes.
Change-Id: Id2101400d885c6938efb6b94f2949722cfbb94ae
Reviewed-on: https://gem5-review.googlesource.com/5481
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
|
|
These had been marked as non-speculative so that their execute
functions would only be called if the instruction should really be
executed. Instead, we can return faults which will cause the same
behavior when the instruction is committed and let the instruction
execute as normal.
Change-Id: I39fa5073e93399424144724b99bdc12070e42286
Reviewed-on: https://gem5-review.googlesource.com/5465
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
|
|
These are simple classes which don't need to be in the ISA description.
Change-Id: Ia0bb45f50c4da2536855efcb3c17c7780b431332
Reviewed-on: https://gem5-review.googlesource.com/5464
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
|
|
The only thing the Unknown format does is return an instance of this
class, so there's no reason to have it in the ISA description.
Change-Id: I3f8187b1450a8622a974c030c0cb552b26f6b5f0
Reviewed-on: https://gem5-review.googlesource.com/5463
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
|
|
The Nop format mostly just made instructions that inherited from the
Nop base class but with different mnemonics, so there doesn't need
to be very much dynamic content.
Change-Id: I1cf5e25ca8372f9b71f56d49756879c7545c9f6c
Reviewed-on: https://gem5-review.googlesource.com/5462
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
|
|
These are for the trap and branch instructions.
Change-Id: Idedab6f3e6c6c954c1f8a36dae52976cf25ad394
Reviewed-on: https://gem5-review.googlesource.com/5461
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
|
|
These classes are just used as base classes for other instructions
and don't need to be part of the ISA definition. Pull them into
standard C++ files.
Change-Id: If3e0bd82b1e676f20459bc0293fbda49de66b554
Reviewed-on: https://gem5-review.googlesource.com/5422
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
|
|
Change the definition of PMU events in order to integrate events not
cannot easily be represented by probe points. The software
increment event is now defined as a special type with its separate
implementation in pmu.cc and pmu.hh.
Change-Id: I43874b9641bf38c54f6ba2c26386542b6a73e282
Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5764
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: I09531e9992e045254e5ee989dd11ccabbf84e4ce
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5763
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Move the code responsible for performing the actual probe point notify
into BaseCPU. Use BaseCPU activateContext and suspendContext to keep
track of sleep cycles. Create a probe point (ppActiveCycles) that does
not count cycles where the processor was asleep. Rename ppCycles
to ppAllCycles to reflect its nature.
Change-Id: I1907ddd07d0ff9f2ef22cc9f61f5f46c630c9d66
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5762
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
|
|
This fixes a fatal already mapped error in
FuncPageTable::allocate that occurs in some cases
when restoring from a checkpoint.
Change-Id: Ib726a69358118626663e42b7f14889b0d3a98de0
Reported-by: Ruohuang Zheng <zhengruohuang@gmail.com>
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/5901
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
This patch is fixing the Aarch32 MCR/MRC disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the coprocessor register name
Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5862
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
This patch is fixing the Aarch64 MSR/MRS disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the system register name
Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5861
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Suspending the current thread context while draining due to a quiesce
pseudo instruction (for example a wfi instruction) could deadlock the
cpu and prevent it from successfully draining. This change ensures
that the cpu is not draining before suspending the thread context.
Change-Id: I7c019847f5a870d4bc9ce2b19936bc3dc45e5fd7
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5881
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Events were not being attached to counters after a checkpoint resume.
By not storing the enable private variable from the stored state the
recreation of the event to counter association is automatically carried.
The enable state is stored in the reg_pmcnten.
Change-Id: I46344df0882a9050c900efb2e8996d64dbfbf297
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5761
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Add the power_gating_on_idle option to control whether a core
automatically enters the power gated state. The default behaviour is
to transition to clock gated when idle, but not to power gated. When
this option is set to true, the core automatically transitions to the
power gated state after a configurable latency.
Change-Id: Ida98c7fc532de4140d0e511c25613769b47b3702
Reviewed-on: https://gem5-review.googlesource.com/5741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
If the CPU has been clock gated for a sufficient amount of time
(configurable via pwrGatingLatency), the CPU will go into the OFF
power state. This does not model hardware, just behaviour.
Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3969
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Also, do some minor refactoring to use a BitUnion to pull apart
condition codes, etc.
Change-Id: I0c88878b07a731d0c0fe30f264f53dd795db99ae
Reviewed-on: https://gem5-review.googlesource.com/5421
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
|
|
A recent serial device refactoring changed the name of the parameter
that the terminal device gets attached to on the UART. The x86 and
SPARC platform devices didn't get updated though, and were still using
the old name. This change updates those objects.
Reported-by: Kanad Basu <kanad.kut@gmail.com>
Change-Id: I0824a9df8639062d8561420ea9ffea26b8b7e2e9
Reviewed-on: https://gem5-review.googlesource.com/5781
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
This test has been broken since 70176fecd1ff04 in 2014. The problem was
that the array size in the test was technically not constant because it
was based on an int variable that wasn't declared as const. That
prevented g++ from resolving it as a template parameter. Before the
change mentioned above, the implementation wasn't based on templates.
Change-Id: I6819cf522f9ba4636ac661da368b9bcbae0a813f
Reviewed-on: https://gem5-review.googlesource.com/5821
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
Recent Linux kernels for AArch64 have changed their start addresses
but we still want to relocate the kernel to 0x80080000 which
required hacking the load_addr_mask in Realview.py to be 0x7ffffff
from 0xfffffff to mask off the proper number of MSBs to load the
kernel in the desired location. To avoid having to make this change
in the future again, we auto-calculate the load_addr_mask if it is
specified as 0x0 in the System sim-object to find the most restrictive
address mask instead of having the configuration specify it. If the
configuration does specify the address mask, we use it instead of
auto-calculating.
Change-Id: I18aabb5d09945c6e3e3819c9c8036ea24b6c35cf
Signed-off-by: Geoffrey Blake <Geoffrey.Blake@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2323
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
|
|
Added a check to avoid unlocking/locking the same event queue. Also,
added an optional parameter to enable the migration to be skipped. This
can be useful to disable the synchronization for certain runtime
conditions.
Change-Id: I4b03b3ffff4f9503153cd41dd8aa78705bf16cc4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5730
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
This patch syncs the DRAMPower library of gem5 to the
external github (https://github.com/ravenrd/DRAMPower).
The version pulled in is the commit:
90d6290f802c29b3de9e10233ceee22290907ce6
from 30th Oct. 2016.
This change also modifies the DRAM Ctrl interaction with the
DRAMPower, due to changes in the lib API in the above version.
Previously multiple functions were called to prepare the power
lib before calling the function that would calculate the enery. With
the new API, these functions are encompassed inside the function to
calculate the energy and therefore should now be removed from the
DRAM controller.
The other key difference is the introduction of a new function called
calcWindowEnergy which can be useful for any system that wants
to do measurements over intervals. For gem5 DRAM ctrl that means we
now need to accumulate the window energy measurements into the total
stat.
Change-Id: I3570fff2805962e166ff2a1a3217ebf2d5a197fb
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5724
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
This patch allows the user to specify more than one
power model for any given Clocked Object. This is
useful and some times necessary to properly model
components that have multiple power sources (or
subcomponents) but gem5 doesn't model them.
The ideal solution would be to have a DictParam
to replace the VectorParam so each model can have
a name and can be identified in the stats file.
Change-Id: I4080a7054a16b56069c44750a7a9ce4e674cdf9d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5733
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
When ignoring writes to the Dummy ISA device (DummyISADevice),
additionally print the value being ignored in the diagnostic.
Sometimes it is useful to know exactly what we are dropping ...
Change-Id: I9a01623611f0da0aa12b065fbb2031aa27e2c036
Signed-off-by: Sean McGoogan <Sean.McGoogan@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5731
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: I5bbf36ef21ac14d9edf68ec6766d33f88e84d308
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5729
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
There are cases where it is desirable to load a kernel and a set of
additional objects. This can, for example, be useful for testing where
the bootstrap code can be loaded from one object (the kernel) and the
test proper from another.
This changeset adds this functionality by adding a kernel_extras
vector parameter to the System class. Object files in this vector are
loaded in order after the kernel when running in full system mode.
Change-Id: I06f57c6a65a17b02eb4267bed0aa829f21bcfa3b
Reviewed-on: https://gem5-review.googlesource.com/5703
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
DSB Instruction shouldn't flush the pipeline, hence the IsSquashAfter
attribute will be removed for either the 32 and 64 bit version.
Change-Id: I98b2b8bc78aa28445ed1a9b5f34645f8d71616ad
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5363
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Writes to DCCMVAC (Data Cache line Clean by VA to PoC) system register
shouldn't flush the pipeline as a result of the operation. This addition
was wrongly introduced for supporting self-modifying code. Software
barriers should be used instead.
Change-Id: Idf0c27d2e49ca01be19888ae5523b8f8eaefa7b3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5362
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
This Patch is removing the FlushPipe ArmFault, which was used for
flushing the pipeline in favour of the general IsSquashAfter StaticInstr
flag. Using a fault was preventing tracers from tracing barriers like
ISB and from adding them to the instruction count
Change-Id: I176e9254eca904694f2f611eb486c55e50ec61ff
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5361
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
This patch introduces the ARM A32/T32/A64 CRC Instructions, which are
mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as
follows:
1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32
2) The instructions support predication in Aarch32
3) Using R15(PC) as source/dest operand is permitted in Aarch32
Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5521
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: I017852eac183fac3f914fdb96d7e72a56ea9d682
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5121
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
This type expects values in joules (J).
Change-Id: I77a3a4f1c19443f573d5fe7a84d5abd954ce1603
Reviewed-on: https://gem5-review.googlesource.com/5625
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
This type was defined, but it was never added to __all__.
Change-Id: I5414829a9562790416f5ceab71af01503d142903
Reviewed-on: https://gem5-review.googlesource.com/5624
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: I7299af0e2a6ce9bd2272d6ccb898997336e95e51
Reviewed-on: https://gem5-review.googlesource.com/5623
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
These had a lot of code which duplicated what was already in the
Float param value class. Also, printing into the ini file with "%f"
forces python to truncate values which require more precision than the
fixed float format supports.
Change-Id: Iad9623b71a31d17b69c184082585dcbb881eaa20
Reviewed-on: https://gem5-review.googlesource.com/5622
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
ARMv8 Tracers might want to be able to read the intWidth field of the
ArmStaticInst object. The field is specifying the bit width of the
integer registers used by the current instruction.
Change-Id: Iaee3123823a2c7380917001c453377c1c12e54a7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5661
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
This patch corrects the encoding of the HVC (Hypervisor Call) for the
T32 instruction set.
Change-Id: I6f77eaf5c586697e9ccd588419c61e6d90c6c7bf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chuan Zhu <chuan.zhu@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5541
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
|
|
The python conversion module was really repetitive and fragmented,
where some types of conversions use common code, and some use hand
written case statements which did something very similar. Also, some
types like Voltage could only handle V and mV but no other scaling
prefix.
This change restructures the module to centralize a lot of the unit
handling code into toFloat, and makes the various other functions use
it.
Change-Id: Ic8529203cc226c9b551b8535a444e3f2f25ad1eb
Reviewed-on: https://gem5-review.googlesource.com/5621
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
