summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
timing mode still broken. configs/example/memtest.py: Revamp options. src/cpu/memtest/memtest.cc: No need for memory initialization. No need to make atomic response... memory system should do that now. src/cpu/memtest/memtest.hh: MemTest really doesn't want to snoop. src/mem/bridge.cc: checkFunctional() cleanup. src/mem/bus.cc: src/mem/bus.hh: src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.cc: src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/coherence_protocol.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/miss/SConscript: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: src/mem/packet.cc: src/mem/packet.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/tport.cc: More major reorg. Seems to work for atomic mode now, timing mode still broken. --HG-- extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
2007-05-29Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 26921dad179699b7868768361143aaa8d790b8fc
2007-05-30tport.cc:Steve Reinhardt
Oops... forgot to update call site after changing function argument semantics. src/mem/tport.cc: Oops... forgot to update call site after changing function argument semantics. --HG-- extra : convert_revision : 9234b991dc678f062d268ace73c71b3d13dd17dc
2007-05-29Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 72c6f2ce7e9e2b46e59711a2c3cfe770c243018e
2007-05-29A little more cleanup & refactoring of SimpleTimingPort.Steve Reinhardt
Make it a better base class for cache ports. --HG-- extra : convert_revision : 37d6de11545a68c1a7d11ce33fe5971c51434ee4
2007-05-28Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 6f462916cb0eb309b6799e94fbf07629abb50eba
2007-05-28Restructure SimpleTimingPort a bit:Steve Reinhardt
- factor out checkFunctional() code so it can be called from derived classes - use EventWrapper for sendEvent, move event handling code from event to port where it belongs - make sendEvent a pointer so derived classes can override it - replace std::pair with new class for readability --HG-- extra : convert_revision : 5709de2daacfb751a440144ecaab5f9fc02e6b7a
2007-05-28Reformat comments to meet line length restriction.Steve Reinhardt
--HG-- extra : convert_revision : 24c00ec4904d9fb4d6e39521e0ff8b8f60d60f6a
2007-05-28Remove unnecessary include of physical.hh.Steve Reinhardt
--HG-- extra : convert_revision : bccafe884e58a55b02ff408448e6644196e439a4
2007-05-27Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : fba7efd444e1ca9738385dd4662a33feab357e79
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-26Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : f940480672861185a494f3fae1bfca13d31fed9f
2007-05-26Get rid of GNU libelf and its autoconf nastiness and replaceNathan Binkert
it with FreeBSD's implementation --HG-- extra : convert_revision : ef9c4551b9a6b54b76a89f286ff9804c55790621
2007-05-26Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : c2540bfd34eb5a6f41cb15ffe50f8ec72f80abb1
2007-05-24Update to ply 2.3Nathan Binkert
ext/ply/ply/lex.py: ext/ply/ply/yacc.py: ext/ply/CHANGES: ext/ply/README: ext/ply/TODO: ext/ply/doc/ply.html: ext/ply/example/ansic/clex.py: ext/ply/example/ansic/cparse.py: ext/ply/example/calc/calc.py: ext/ply/example/hedit/hedit.py: ext/ply/example/optcalc/calc.py: ext/ply/test/README: ext/ply/test/calclex.py: ext/ply/test/lex_doc1.exp: ext/ply/test/lex_doc1.py: ext/ply/test/lex_dup1.exp: ext/ply/test/lex_dup1.py: ext/ply/test/lex_dup2.exp: ext/ply/test/lex_dup2.py: ext/ply/test/lex_dup3.exp: ext/ply/test/lex_dup3.py: ext/ply/test/lex_empty.py: ext/ply/test/lex_error1.py: ext/ply/test/lex_error2.py: ext/ply/test/lex_error3.exp: ext/ply/test/lex_error3.py: ext/ply/test/lex_error4.exp: ext/ply/test/lex_error4.py: ext/ply/test/lex_hedit.exp: ext/ply/test/lex_hedit.py: ext/ply/test/lex_ignore.exp: ext/ply/test/lex_ignore.py: ext/ply/test/lex_re1.exp: ext/ply/test/lex_re1.py: ext/ply/test/lex_rule1.py: ext/ply/test/lex_token1.py: ext/ply/test/lex_token2.py: ext/ply/test/lex_token3.py: ext/ply/test/lex_token4.py: ext/ply/test/lex_token5.exp: ext/ply/test/lex_token5.py: ext/ply/test/yacc_badargs.exp: ext/ply/test/yacc_badargs.py: ext/ply/test/yacc_badprec.exp: ext/ply/test/yacc_badprec.py: ext/ply/test/yacc_badprec2.exp: ext/ply/test/yacc_badprec2.py: ext/ply/test/yacc_badrule.exp: ext/ply/test/yacc_badrule.py: ext/ply/test/yacc_badtok.exp: ext/ply/test/yacc_badtok.py: ext/ply/test/yacc_dup.exp: ext/ply/test/yacc_dup.py: ext/ply/test/yacc_error1.exp: ext/ply/test/yacc_error1.py: ext/ply/test/yacc_error2.exp: ext/ply/test/yacc_error2.py: ext/ply/test/yacc_error3.exp: ext/ply/test/yacc_error3.py: ext/ply/test/yacc_inf.exp: ext/ply/test/yacc_inf.py: ext/ply/test/yacc_missing1.exp: ext/ply/test/yacc_missing1.py: ext/ply/test/yacc_nodoc.exp: ext/ply/test/yacc_nodoc.py: ext/ply/test/yacc_noerror.exp: ext/ply/test/yacc_noerror.py: ext/ply/test/yacc_nop.exp: ext/ply/test/yacc_nop.py: ext/ply/test/yacc_notfunc.exp: ext/ply/test/yacc_notfunc.py: ext/ply/test/yacc_notok.exp: ext/ply/test/yacc_notok.py: ext/ply/test/yacc_rr.exp: ext/ply/test/yacc_rr.py: ext/ply/test/yacc_simple.exp: ext/ply/test/yacc_simple.py: ext/ply/test/yacc_sr.exp: ext/ply/test/yacc_sr.py: ext/ply/test/yacc_term1.exp: ext/ply/test/yacc_term1.py: ext/ply/test/yacc_unused.exp: ext/ply/test/yacc_unused.py: ext/ply/test/yacc_uprec.exp: ext/ply/test/yacc_uprec.py: Import patch ply.diff src/arch/isa_parser.py: everything is now within the ply package --HG-- rename : ext/ply/lex.py => ext/ply/ply/lex.py rename : ext/ply/yacc.py => ext/ply/ply/yacc.py extra : convert_revision : fca8deabd5c095bdeabd52a1f236ae1404ef106e
2007-05-22Fix getDeviceAddressRanges() to get snooping right.Steve Reinhardt
--HG-- extra : convert_revision : 2aeab25ef955ab9db7b968786faff227239fbbe4
2007-05-22Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 src/mem/cache/base_cache.hh: Manual conflict resolution. --HG-- extra : convert_revision : 5ebfd7abb4f978caa88bf43d25935869edfc6b9f
2007-05-22memtest.hh:Steve Reinhardt
Fix description string. Minor whitespace cleanup. src/cpu/memtest/memtest.hh: Fix description string. Minor whitespace cleanup. --HG-- extra : convert_revision : 0c7213d088da46de9713ca6beabc30523ccb1c8c
2007-05-22Another pass of minor changes in preparation for new protocol.Steve Reinhardt
src/mem/cache/cache_impl.hh: src/mem/cache/coherence/simple_coherence.hh: Get rid of old invalidate propagation logic in preparation for new multilevel snoop protocol. src/mem/cache/coherence/coherence_protocol.cc: L2 cache now has protocol, so protocol must handle ReadExReq coming in from the CPU side. src/mem/cache/miss/mshr_queue.cc: Assertion is failing, so let's take it out for now. src/mem/packet.cc: src/mem/packet.hh: Add WritebackAck command. Reorganize enum to put responses next to corresponding requests. Get rid of unused WriteReqNoAck. --HG-- extra : convert_revision : 24c519846d161978123f9aa029ae358a41546c73
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
--HG-- extra : convert_revision : 832e52ba80cbab2f5bb6d5b5977a499d41b4d638
2007-05-20Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : a8efe71a50b9ae480c5ad0aabd7aa9ba22bc2968
2007-05-20Add new EventWrapper constructor that takes a Tick valueSteve Reinhardt
and schedules the event immediately. --HG-- extra : convert_revision : a84e729a5ef3632cbe6cff858c453c782707d983
2007-05-20Insist that PhysicalMemory object have at least one connection.Steve Reinhardt
--HG-- extra : convert_revision : 36c33d25a3b23ac2094577aa504c24fac0f3ffcc
2007-05-18Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 src/mem/bridge.cc: SCCS merged --HG-- extra : convert_revision : 9492be56a305afe88f28a77c3b23e80ce6aa81b3
2007-05-18First set of changes for reorganized cache coherence support.Steve Reinhardt
Compiles but doesn't work... committing just so I can merge (stupid bk!). src/mem/bridge.cc: Get rid of SNOOP_COMMIT. src/mem/bus.cc: src/mem/packet.hh: Get rid of SNOOP_COMMIT & two-pass snoop. First bits of EXPRESS_SNOOP support. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/miss_queue.cc: src/mem/cache/prefetch/base_prefetcher.cc: Big reorg of ports and port-related functions & events. src/mem/cache/cache.cc: src/mem/cache/cache_builder.cc: src/mem/cache/coherence/SConscript: Get rid of UniCoherence object. --HG-- extra : convert_revision : 7672434fa3115c9b1c94686f497e57e90413b7c3
2007-05-19Oops... some places in C++ explicitly ask for a "functional"Steve Reinhardt
port. It would be better to move this to python IMO but for now I'll stick in a compatibility hack. --HG-- extra : convert_revision : a81a29cbd43becd0e485559eb7b2a31f7a0b082d
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
configs/example/memtest.py: PhysicalMemory has vector of uniform ports instead of one special one. Other updates to fix obsolete brokenness. src/mem/physical.cc: src/mem/physical.hh: src/python/m5/objects/PhysicalMemory.py: Have vector of uniform ports instead of one special one. src/python/swig/pyobject.cc: Add comment. --HG-- extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1
2007-05-15Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 32dc1bec7fdb1ecb8879ed2dd745c4b23929aeab
2007-05-15hopefully the final hacky change to make the bus bridge work okAli Saidi
cache blocks that get dmaed ARE NOT marked invalid in the caches so it's a performance issue here src/mem/bridge.cc: src/mem/bridge.hh: hopefully the final hacky change to make the bus bridge work ok --HG-- extra : convert_revision : 62cbc65c74d1a84199f0a376546ec19994c5899c
2007-05-14Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 8a501917daf81021212d136b4ebbfa059b452a13
2007-05-14Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : e445097240af7b4e73efaca855cd1f217cf00313
2007-05-14couple more bug fixes for intel nicAli Saidi
src/dev/i8254xGBe.cc: src/dev/i8254xGBe.hh: couple more bug fixes --HG-- extra : convert_revision : ae5b806528c1ec06f0091e1f6e50fc0721057ddb
2007-05-14add uglyiness to fix dmasAli Saidi
src/dev/io_device.cc: extra printing and assertions src/mem/bridge.hh: deal with packets only satisfying part of a request by making many requests src/mem/cache/cache_impl.hh: make the cache try to satisfy a functional request from the cache above it before checking itself --HG-- extra : convert_revision : 1df52ab61d7967e14cc377c560495430a6af266a
2007-05-13Eliminate unused PacketPtr from BaseCache'sSteve Reinhardt
RequestEvent and ResponseEvent. Compiles but not tested. --HG-- extra : convert_revision : cc791e7adea5b0406e986a0076edba51856b9105
2007-05-13Split BaseCache::CacheEvent into RequestEvent and ResponseEvent.Steve Reinhardt
Compiles but not tested. --HG-- extra : convert_revision : 4e1e28c4b87721ccfcf35a5ea62c1fa324acbaf9
2007-05-13fix handling of atomic packetsAli Saidi
fix up code for counting requests and responses --HG-- extra : convert_revision : 0d70981ee41c5d9c36cad01bd505281a096f6119
2007-05-11Move full CPU sim object stuff into the encumbered directoryNathan Binkert
--HG-- extra : convert_revision : 788068dd4f4994d0016dba7e8705359d45a3a45c
2007-05-11Float should have a c++ param typeNathan Binkert
--HG-- extra : convert_revision : 150bbe7f31aafb43a75195fc2a365fb3c0ec5673
2007-05-11total should be the sum of the vector result of an operation,Nathan Binkert
not sum the operands and then apply the operation. --HG-- extra : convert_revision : 06486e59b3dd9588b458ef45c341cc4f2554dc09
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
set the latency parameter in terms of a latency add caches to tsunami-simple configs configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs --HG-- extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1
2007-05-10Merge zizzer:/bk/newmemAli Saidi
into pb15.local:/Users/ali/work/m5.newmem.zeep tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt: the new version of this is what we want --HG-- extra : convert_revision : 204df6f8181df81e423def4695cd81544c485c47
2007-05-10add/update parameters for bus bridgeAli Saidi
--HG-- extra : convert_revision : 063f757fbfa2c613328ffa70e556f8926623fa91
2007-05-09couple of updates in the intel nicAli Saidi
--HG-- extra : convert_revision : da68e5e6411000d9d5247f769ee528a443286c61
2007-05-09update for new reschedule semanticsAli Saidi
--HG-- extra : convert_revision : 8c18b2513d638f67cc096e7f1483b47390a374ca
2007-05-09undo my previous bus change, it can make the bus deadlock.. so it still ↵Ali Saidi
constantly reschedules itself --HG-- extra : convert_revision : b5ef1aa0a6a2e32bd775d2dbcad9cd9505ad9b78
2007-05-09add a backoff algorithm when nacks are received by devicesAli Saidi
add seperate response buffers and request queue sizes in bus bridge add delay to respond to a nack in the bus bridge src/dev/i8254xGBe.cc: src/dev/ide_ctrl.cc: src/dev/ns_gige.cc: src/dev/pcidev.hh: src/dev/sinic.cc: add backoff delay parameters src/dev/io_device.cc: src/dev/io_device.hh: add a backoff algorithm when nacks are received. src/mem/bridge.cc: src/mem/bridge.hh: add seperate response buffers and request queue sizes add a new parameters to specify how long before a nack in ready to go after a packet that needs to be nacked is received src/mem/cache/cache_impl.hh: assert on the src/mem/tport.cc: add a friendly assert to make sure the packet was inserted into the list --HG-- extra : convert_revision : 3595ad932015a4ce2bb72772da7850ad91bd09b1
2007-05-09fix the translating ports so it can add a page on a faultAli Saidi
--HG-- extra : convert_revision : 56f6f2cbf4e92b7f2dd8c9453831fab86d83ef80
2007-05-09Merge zizzer:/bk/newmemAli Saidi
into udhcp-macvpn-703.public.engin.umich.edu:/Users/ali/work/m5.newmem --HG-- extra : convert_revision : e977c5b194954774b6503484797f1c1e0eb4e425
2007-05-09bit_val was being used directly in the statement in return. If type B had ↵Ali Saidi
fewer bits than last, bit_val << last would get the wrong answer. src/base/bitfield.hh: bit_val was being used directly in the statement in return. If type B had fewer bits than last, bit_val << last would get the wrong answer. --HG-- extra : convert_revision : cbc43ccd139f82ebbd65f30af5d05b87c4edac64
2007-05-07the bridge never returns false when recvTiming() is called on its ports now, ↵Ali Saidi
it always returns true and nacks the packet if there isn't sufficient buffer space fix the timing cpu to handle receiving a nacked packet src/cpu/simple/timing.cc: make the timing cpu handle receiving a nacked packet src/mem/bridge.cc: src/mem/bridge.hh: the bridge never returns false when recvTiming() is called on its ports now, it always returns true and nacks the packet if there isn't sufficient buffer space --HG-- extra : convert_revision : 5e12d0cf6ce985a5f72bcb7ce26c83a76c34c50a
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 10:08:59 +0000