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2008-11-10SCons: Allow top level directory of EXTRAS able to contain SConscripts.Nathan Binkert
The current EXTRAS will fail if the top level directory pointed to by EXTRAS has a SConscript file in it. We allow this by including the directory name of the EXTRA in the build directory which prevents a clash between src/SConscript and extra/SConscript. Maintain compatibility with older uses of EXTRAS by adding a -I for each top level extra directory.
2008-11-10pseudo inst: Add rpns (read processor nanoseconds) instruction.Nathan Binkert
This instruction basically returns the number of nanoseconds that the CPU has been running.
2008-11-10Clean up the SimpleTimingPort class a little bit.Nathan Binkert
Move the constructor into the .cc file and get rid of the typedef for SendEvent.
2008-11-10clean: Move some stuff from the hh file to the cc file.Nathan Binkert
2008-11-10python: Fix the reference counting for python events placed on the eventq.Nathan Binkert
We need to add a reference when an object is put on the C++ queue, and remove a reference when the object is removed from the queue. This was not happening before and caused a memory problem.
2008-11-10O3CPU: Make the instcount debugging stuff per-cpu.Clint Smullen
This is to prevent the assertion from firing if you have a large multicore. Also make sure that it's not compiled in when NDEBUG is defined
2008-11-10mem: update stuff for changes to Packet and RequestNathan Binkert
2008-11-10style: clean up the Packet stuffNathan Binkert
2008-11-10flags: Provide an object for managing boolean flags for an object.Nathan Binkert
In many cases it might be preferable to use bitset, but this object allows the user more easily manipulate groups of flags because the underlying type (e.g. uint64_t) is exposed.
2008-11-10safe_cast: add a new cast function for casts that should always succeed.Nathan Binkert
In DEBUG mode, this does a dynamic_cast and asserts that the result is non null. Otherwise, it just does a static_cast. Again, this is only intended for cases where the cast should always succeed and what's desired is a debugging check to make sure.
2008-11-10DmaDevice: fix minor type in error message.Steve Reinhardt
2008-11-10mem: Assert that requests have non-negative size.Steve Reinhardt
Would have saved me much debugging time if these had been in there previously.
2008-11-10Cache: Refactor packet forwarding a bit.Steve Reinhardt
Makes adding write-through operations easier.
2008-11-09CPU: Make unaligned accesses work in the timing simple CPU.Gabe Black
2008-11-09X86: Fix completeAcc get call.Gabe Black
2008-11-09X86: Make the timing simple CPU handle variable length instructions.Gabe Black
2008-11-05Fix a few more places where the context stuff wasn't changedNathan Binkert
2008-11-05Fix SPARC_FS compileLisa Hsu
2008-11-05Right now a single thread cpu 1 could get assigned context Id != 1, dependingLisa Hsu
on the order in which it's registered with the system. To make them match, here is a little change.
2008-11-04decouple eviction from insertion in the cache.Lisa Hsu
2008-11-04Change the findBlock(addr, lat) to accessBlock, which I think has better ↵Lisa Hsu
connotations for what is really happening and how it should be used.
2008-11-04get rid of all instances of readTid() and getThreadNum(). Unify and eliminateLisa Hsu
redundancies with threadId() as their replacement.
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate.
2008-11-02Make it so that all thread contexts are registered with the System, even inLisa Hsu
SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration.
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch.
2008-10-27CPU: The API change to EventWrapper did not get propagated to the entirety ↵Clint Smullen
of TimingSimpleCPU. The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning. Signed-off By: Ali Saidi
2008-10-27Checkpointing: createCountedDrain function, it was only returning an Event, ↵Clint Smullen
which does not expose a setCount method to Python. Signed-off By: Ali Saidi
2008-10-23s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos inLisa Hsu
comments.
2008-10-23probe function no longer used anywhere.Lisa Hsu
2008-10-23remove the totally obsolete split cacheLisa Hsu
2008-10-21style: Use the correct m5 style for things relating to interrupts.Nathan Binkert
2008-10-20O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. ↵Ali Saidi
Removing hwrei causes the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal call sys and thus the translation fails because the user is attempting to access a super page address. Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs. Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were removed since a great deal of manual patching would be required to only remove the hwrei change.
2008-10-19Automated merge with ssh://daystrom.m5sim.org//z/repo/m5Lisa Hsu
2008-10-16need to add packet_access.hh in order to get tempalte definitionNathan Binkert
2008-10-16get rid of local variable that's only used in an assert so fast compilesNathan Binkert
2008-10-16Automated merge with ssh://daystrom.m5sim.org//z/repo/m5Lisa Hsu
2008-10-14This function declaration isn't used anywhere.Lisa Hsu
HG: user: Lisa Hsu <hsul@eecs.umich.edu> HG: branch default HG: changed src/mem/cache/cache.hh
2008-10-14eventq: make python events actually workNathan Binkert
2008-10-14eventq: revert code for unserializing events.Nathan Binkert
Since I never implemented a proper solution, put it back to something that at least works for now. Once I add more event queues, I'll have to really fix this though
2008-10-12CPU: Explain why some code is commented out.Gabe Black
2008-10-12Get rid of some commented out code.Gabe Black
2008-10-12X86: Set the delayed commit flag in x86 microops appropriately.Gabe Black
2008-10-12X86: Make the local APIC timer event generate an interrupt.Gabe Black
2008-10-12X86: Implement the EOI register in the local APIC.Gabe Black
2008-10-12X86: Add some DPRINTFs to the local APIC.Gabe Black
2008-10-12X86: Make auto eoi mode work in the I8259 PIC.Gabe Black
2008-10-12X86: Make non-specific EOI commands work.Gabe Black
2008-10-12X86: Make the I8259 PIC accept a specific EOI command.Gabe Black
2008-10-12X86: Fix the segment setting code in IRET, and make it restore the flags.Gabe Black
2008-10-12X86: Panic when an unimplemented fault is invoked, rather than spinning foreverGabe Black